From 3da693b7d98782437c25b1f6c2d0efb3a398246b Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Thu, 21 Jun 2018 22:50:51 -0400 Subject: [PATCH] ac/surface: move cmask_size/alignment into radeon_surf cmask_size is changed to uint32_t because it can't be greater than 4GB. Reviewed-by: Timothy Arceri --- src/amd/common/ac_surface.c | 6 +++--- src/amd/common/ac_surface.h | 16 ++++++++-------- src/amd/vulkan/radv_image.c | 4 ++-- src/gallium/drivers/radeonsi/si_texture.c | 6 +++--- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 6a335111314..f5f88c1e791 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -1286,8 +1286,8 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib, surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned; surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned; - surf->u.gfx9.cmask_size = cout.cmaskBytes; - surf->u.gfx9.cmask_alignment = cout.baseAlign; + surf->cmask_size = cout.cmaskBytes; + surf->cmask_alignment = cout.baseAlign; } } @@ -1428,7 +1428,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib, surf->htile_slice_size = 0; surf->u.gfx9.surf_offset = 0; surf->u.gfx9.stencil_offset = 0; - surf->u.gfx9.cmask_size = 0; + surf->cmask_size = 0; /* Calculate texture layout information. */ r = gfx9_compute_miptree(addrlib, config, surf, compressed, diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index 864b5bad529..01f1cc8dbac 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -150,9 +150,6 @@ struct gfx9_surf_layout { uint16_t dcc_pitch_max; /* (mip chain pitch - 1) */ uint64_t stencil_offset; /* separate stencil */ - uint64_t cmask_size; - - uint32_t cmask_alignment; }; struct radeon_surf { @@ -196,17 +193,20 @@ struct radeon_surf { uint64_t surf_size; uint64_t fmask_size; + uint32_t surf_alignment; + uint32_t fmask_alignment; + /* DCC and HTILE are very small. */ uint32_t dcc_size; - uint32_t htile_size; + uint32_t dcc_alignment; + uint32_t htile_size; uint32_t htile_slice_size; - - uint32_t surf_alignment; - uint32_t fmask_alignment; - uint32_t dcc_alignment; uint32_t htile_alignment; + uint32_t cmask_size; + uint32_t cmask_alignment; + union { /* R600-VI return values. * diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 24f974ac496..826f898d281 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -772,8 +772,8 @@ radv_image_get_cmask_info(struct radv_device *device, unsigned cl_width, cl_height; if (device->physical_device->rad_info.chip_class >= GFX9) { - out->alignment = image->surface.u.gfx9.cmask_alignment; - out->size = image->surface.u.gfx9.cmask_size; + out->alignment = image->surface.cmask_alignment; + out->size = image->surface.cmask_size; return; } diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index cb6cf196148..4ae02669443 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -1050,11 +1050,11 @@ void si_print_texture_info(struct si_screen *sscreen, } if (tex->cmask.size) { - u_log_printf(log, " CMask: offset=%"PRIu64", size=%"PRIu64", " + u_log_printf(log, " CMask: offset=%"PRIu64", size=%u, " "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n", tex->cmask.offset, - tex->surface.u.gfx9.cmask_size, - tex->surface.u.gfx9.cmask_alignment, + tex->surface.cmask_size, + tex->surface.cmask_alignment, tex->surface.u.gfx9.cmask.rb_aligned, tex->surface.u.gfx9.cmask.pipe_aligned); } -- 2.30.2