From 3dba8516d6468866f2534f517358a6243eb0995e Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Tue, 19 Jul 2016 19:00:19 -0700 Subject: [PATCH] i965: Move VS load_input handling to nir_emit_vs_intrinsic(). TCS/TES/GS and now FS all handle these in stage-specific functions. CS don't have inputs, so VS was the only one left using this code. Move it to the VS-specific function for clarity. Signed-off-by: Kenneth Graunke Reviewed-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 61 ++++++++++++------------ 1 file changed, 30 insertions(+), 31 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index 22cba8c32db..4d4c94a55bd 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp @@ -2358,6 +2358,36 @@ fs_visitor::nir_emit_vs_intrinsic(const fs_builder &bld, break; } + case nir_intrinsic_load_input: { + fs_reg src = fs_reg(ATTR, instr->const_index[0], dest.type); + unsigned num_components = instr->num_components; + enum brw_reg_type type = dest.type; + + nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]); + assert(const_offset && "Indirect input loads not allowed"); + src = offset(src, bld, const_offset->u32[0]); + + for (unsigned j = 0; j < num_components; j++) { + bld.MOV(offset(dest, bld, j), offset(src, bld, j)); + } + + if (type == BRW_REGISTER_TYPE_DF) { + /* Once the double vector is read, set again its original register + * type to continue with normal execution. + */ + src = retype(src, type); + dest = retype(dest, type); + } + + if (type_sz(src.type) == 8) { + shuffle_32bit_load_result_to_64bit_data(bld, + dest, + retype(dest, BRW_REGISTER_TYPE_F), + instr->num_components); + } + break; + } + default: nir_emit_intrinsic(bld, instr); break; @@ -3968,37 +3998,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr break; } - case nir_intrinsic_load_input: { - fs_reg src = fs_reg(ATTR, instr->const_index[0], dest.type); - unsigned num_components = instr->num_components; - enum brw_reg_type type = dest.type; - - nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]); - assert(const_offset && "Indirect input loads not allowed"); - src = offset(src, bld, const_offset->u32[0]); - - for (unsigned j = 0; j < num_components; j++) { - bld.MOV(offset(dest, bld, j), offset(src, bld, j)); - } - - if (type == BRW_REGISTER_TYPE_DF) { - /* Once the double vector is read, set again its original register - * type to continue with normal execution. - */ - src = retype(src, type); - dest = retype(dest, type); - } - - if (type_sz(src.type) == 8) { - shuffle_32bit_load_result_to_64bit_data(bld, - dest, - retype(dest, BRW_REGISTER_TYPE_F), - instr->num_components); - } - - break; - } - case nir_intrinsic_store_ssbo: { assert(devinfo->gen >= 7); -- 2.30.2