From 3dbb4dcecd9a93e308c01ec61a725b9a3c9d2381 Mon Sep 17 00:00:00 2001 From: James E Wilson Date: Fri, 7 Oct 2005 17:39:09 -0700 Subject: [PATCH] Fix gcc.dg/vect/vect-shift-1.c failure. * config/ia64/vect.md (ashl3, ashr3, lshr3): Use DImode not VECINT24 for operand 2. From-SVN: r105113 --- gcc/ChangeLog | 3 +++ gcc/config/ia64/vect.md | 6 +++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a16029498b7..86ba1b278df 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,8 @@ 2005-10-07 James E. Wilson + * config/ia64/vect.md (ashl3, ashr3, lshr3): Use + DImode not VECINT24 for operand 2. + PR target/23644 * doc/invoke.texi (IA-64 Options, item -mtune): Renamed from -mtune-arch. diff --git a/gcc/config/ia64/vect.md b/gcc/config/ia64/vect.md index 3d4669bc8bc..94380bfcc49 100644 --- a/gcc/config/ia64/vect.md +++ b/gcc/config/ia64/vect.md @@ -318,7 +318,7 @@ [(set (match_operand:VECINT24 0 "gr_register_operand" "=r") (ashift:VECINT24 (match_operand:VECINT24 1 "gr_register_operand" "r") - (match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))] + (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))] "" "pshl %0 = %1, %2" [(set_attr "itanium_class" "mmshf")]) @@ -327,7 +327,7 @@ [(set (match_operand:VECINT24 0 "gr_register_operand" "=r") (ashiftrt:VECINT24 (match_operand:VECINT24 1 "gr_register_operand" "r") - (match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))] + (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))] "" "pshr %0 = %1, %2" [(set_attr "itanium_class" "mmshf")]) @@ -336,7 +336,7 @@ [(set (match_operand:VECINT24 0 "gr_register_operand" "=r") (lshiftrt:VECINT24 (match_operand:VECINT24 1 "gr_register_operand" "r") - (match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))] + (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))] "" "pshr.u %0 = %1, %2" [(set_attr "itanium_class" "mmshf")]) -- 2.30.2