From 3dca6b51405ae08988b922f619fa63832331b140 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Mon, 4 Oct 2021 20:04:42 +0200 Subject: [PATCH] update test_compldst_multi_mmu.py to use pagetables --- .../test/test_compldst_multi_mmu.py | 35 +++---------------- 1 file changed, 5 insertions(+), 30 deletions(-) diff --git a/src/soc/experiment/test/test_compldst_multi_mmu.py b/src/soc/experiment/test/test_compldst_multi_mmu.py index e8179960..d21d5b91 100644 --- a/src/soc/experiment/test/test_compldst_multi_mmu.py +++ b/src/soc/experiment/test/test_compldst_multi_mmu.py @@ -27,11 +27,8 @@ from soc.experiment.mmu import MMU from nmutil.util import Display from soc.config.loadstore import ConfigMemoryPortInterface +from soc.experiment.test import pagetables -def b(x): # byte-reverse function - return int.from_bytes(x.to_bytes(8, byteorder='little'), - byteorder='big', signed=False) -#FIXME: move to common module def wait_for_debug(sig, event, wait=True, test1st=False): v = (yield sig) @@ -245,7 +242,7 @@ def wb_get(wb, mem): yield def test_scoreboard_regspec_mmu(): - + m = Module() units = {} @@ -263,33 +260,11 @@ def test_scoreboard_regspec_mmu(): sim = Simulator(m) sim.add_clock(1e-6) - sim.add_sync_process(wrap(ldst_sim(dut))) - - # FIXME: this is redundant code - mem = { - 0x10000: # PARTITION_TABLE_2 - # PATB_GR=1 PRTB=0x1000 PRTS=0xb - b(0x800000000100000b), - - 0x30000: # RADIX_ROOT_PTE - # V = 1 L = 0 NLB = 0x400 NLS = 9 - b(0x8000000000040009), - - 0x40000: # RADIX_SECOND_LEVEL - # V = 1 L = 1 SW = 0 RPN = 0 - # R = 1 C = 1 ATT = 0 EAA 0x7 - b(0xc000000000000183), - - 0x1000000: # PROCESS_TABLE_3 - # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13 - b(0x40000000000300ad), - - 0x10004: 0 - - } + mem = pagetables.test1 + sim.add_sync_process(wrap(ldst_sim(dut))) sim.add_sync_process(wrap(wb_get(dut.cmpi.wb_bus(), mem))) - with sim.write_vcd('test_dcbz_addr_zero.vcd'): + with sim.write_vcd('test_scoreboard_regspec_mmu'): sim.run() -- 2.30.2