From 3dcd6975123afc55c7f24f2d48a22719aedcfdc6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 27 May 2021 13:04:10 +0100 Subject: [PATCH] corrections on spblock ack --- src/soc/bus/SPBlock512W64B8W.py | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/soc/bus/SPBlock512W64B8W.py b/src/soc/bus/SPBlock512W64B8W.py index 25f2da74..0a0d483b 100644 --- a/src/soc/bus/SPBlock512W64B8W.py +++ b/src/soc/bus/SPBlock512W64B8W.py @@ -59,11 +59,10 @@ class SPBlock512W64B8W(Elaboratable): with m.If(self.enable): # in case of layout problems # wishbone is active if cyc and stb set wb_active = Signal() - m.d.comb += wb_active.eq(self.bus.cyc & self.bus.stb & - ~self.bus.ack) + m.d.comb += wb_active.eq(self.bus.cyc & self.bus.stb) - # generate ack (no "pipeline" mode here) - m.d.sync += self.bus.ack.eq(wb_active) + # generate ack (no "pipeline" mode here). do "classic" mode + m.d.sync += self.bus.ack.eq(wb_active & ~self.bus.ack) with m.If(wb_active): -- 2.30.2