From 3de11cacf0cb307ff3b4130746732d9db73d7583 Mon Sep 17 00:00:00 2001 From: Matt Turner Date: Sun, 29 Jun 2014 16:02:59 -0700 Subject: [PATCH] i965: Use enum brw_reg_type for register types. Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h | 3 ++- src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +- src/mesa/drivers/dri/i965/brw_fs.h | 4 ++-- src/mesa/drivers/dri/i965/brw_reg.h | 8 ++++---- src/mesa/drivers/dri/i965/brw_shader.cpp | 2 +- src/mesa/drivers/dri/i965/brw_shader.h | 4 ++-- src/mesa/drivers/dri/i965/brw_vec4.h | 4 ++-- 7 files changed, 14 insertions(+), 13 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h index 15a7a0b552b..683f09e681f 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.h +++ b/src/mesa/drivers/dri/i965/brw_blorp.h @@ -26,6 +26,7 @@ #include #include "brw_context.h" +#include "brw_reg.h" #include "intel_mipmap_tree.h" struct brw_context; @@ -299,7 +300,7 @@ struct brw_blorp_blit_prog_key /* Type of the data to be read from the texture (one of * BRW_REGISTER_TYPE_{UD,D,F}). */ - unsigned texture_data_type; + enum brw_reg_type texture_data_type; /* True if the source image is W tiled. If true, the surface state for the * source image must be configured as Y tiled, and tex_samples must be 0. diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 3d10799ae83..2a7c00e7892 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -866,7 +866,7 @@ fs_reg::fs_reg(enum register_file file, int reg) } /** Fixed HW reg constructor. */ -fs_reg::fs_reg(enum register_file file, int reg, uint32_t type) +fs_reg::fs_reg(enum register_file file, int reg, enum brw_reg_type type) { init(); this->file = file; diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index 530e54b7f27..4781079ab8d 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -75,7 +75,7 @@ public: fs_reg(uint32_t u); fs_reg(struct brw_reg fixed_hw_reg); fs_reg(enum register_file file, int reg); - fs_reg(enum register_file file, int reg, uint32_t type); + fs_reg(enum register_file file, int reg, enum brw_reg_type type); fs_reg(class fs_visitor *v, const struct glsl_type *type); bool equals(const fs_reg &r) const; @@ -99,7 +99,7 @@ public: }; static inline fs_reg -retype(fs_reg reg, unsigned type) +retype(fs_reg reg, enum brw_reg_type type) { reg.fixed_hw_reg.type = reg.type = type; return reg; diff --git a/src/mesa/drivers/dri/i965/brw_reg.h b/src/mesa/drivers/dri/i965/brw_reg.h index b2273c3262b..494ce8c4fa5 100644 --- a/src/mesa/drivers/dri/i965/brw_reg.h +++ b/src/mesa/drivers/dri/i965/brw_reg.h @@ -131,7 +131,7 @@ const char *brw_reg_type_letters(unsigned brw_reg_type); * or "structure of array" form: */ struct brw_reg { - unsigned type:4; + enum brw_reg_type type:4; unsigned file:2; unsigned nr:8; unsigned subnr:5; /* :1 in align16 */ @@ -227,7 +227,7 @@ static inline struct brw_reg brw_reg(unsigned file, unsigned nr, unsigned subnr, - unsigned type, + enum brw_reg_type type, unsigned vstride, unsigned width, unsigned hstride, @@ -362,7 +362,7 @@ brw_vecn_reg(unsigned width, unsigned file, unsigned nr, unsigned subnr) } static inline struct brw_reg -retype(struct brw_reg reg, unsigned type) +retype(struct brw_reg reg, enum brw_reg_type type) { reg.type = type; return reg; @@ -424,7 +424,7 @@ brw_uw1_reg(unsigned file, unsigned nr, unsigned subnr) } static inline struct brw_reg -brw_imm_reg(unsigned type) +brw_imm_reg(enum brw_reg_type type) { return brw_reg(BRW_IMMEDIATE_VALUE, 0, diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index fa427334317..58ebd331ef1 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -279,7 +279,7 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg) } -int +enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type) { switch (type->base_type) { diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h index b0908a3c1d1..a5eed91ef22 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.h +++ b/src/mesa/drivers/dri/i965/brw_shader.h @@ -50,7 +50,7 @@ struct backend_reg #endif enum register_file file; /**< Register file: GRF, MRF, IMM. */ - uint8_t type; /**< Register type: BRW_REGISTER_TYPE_* */ + enum brw_reg_type type; /**< Register type: BRW_REGISTER_TYPE_* */ /** * Register number. @@ -166,7 +166,7 @@ void annotation_finalize(struct annotation_info *annotation, unsigned offset); #endif /* __cplusplus */ -int brw_type_for_base_type(const struct glsl_type *type); +enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type); uint32_t brw_conditional_for_comparison(unsigned int op); uint32_t brw_math_function(enum opcode op); const char *brw_instruction_name(enum opcode op); diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h index 331b9b5eaa7..4b6e6382684 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.h +++ b/src/mesa/drivers/dri/i965/brw_vec4.h @@ -117,7 +117,7 @@ public: }; static inline src_reg -retype(src_reg reg, unsigned type) +retype(src_reg reg, enum brw_reg_type type) { reg.fixed_hw_reg.type = reg.type = type; return reg; @@ -176,7 +176,7 @@ public: }; static inline dst_reg -retype(dst_reg reg, unsigned type) +retype(dst_reg reg, enum brw_reg_type type) { reg.fixed_hw_reg.type = reg.type = type; return reg; -- 2.30.2