From 3de4f6c9f0322830a9a1138e64079228ad410061 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 20 Feb 2020 11:35:23 +0100 Subject: [PATCH] ac: add more fields to ac_gpu_info For RGP traces. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/common/ac_gpu_info.c | 54 +++++++++++++++++++++++++++++++++++- src/amd/common/ac_gpu_info.h | 8 ++++++ 2 files changed, 61 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 4454f82f4b5..097e5cfc3c9 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -101,6 +101,40 @@ static uint64_t fix_vram_size(uint64_t size) return align64(size, 256*1024*1024); } +static uint32_t +get_l2_cache_size(enum radeon_family family) +{ + switch (family) { + case CHIP_KABINI: + case CHIP_STONEY: + return 128 * 1024; + case CHIP_OLAND: + case CHIP_HAINAN: + case CHIP_ICELAND: + return 256 * 1024; + case CHIP_PITCAIRN: + case CHIP_VERDE: + case CHIP_BONAIRE: + case CHIP_KAVERI: + case CHIP_POLARIS12: + case CHIP_CARRIZO: + return 512 * 1024; + case CHIP_TAHITI: + case CHIP_TONGA: + return 768 * 1024; + break; + case CHIP_HAWAII: + case CHIP_POLARIS11: + return 1024 * 1024; + case CHIP_FIJI: + case CHIP_POLARIS10: + return 2048 * 1024; + break; + default: + return 4096 * 1024; + } +} + bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, struct amdgpu_gpu_info *amdinfo) @@ -311,6 +345,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, /* Set chip identification. */ info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */ + info->pci_rev_id = amdinfo->pci_rev_id; info->vce_harvest_config = amdinfo->vce_harvest_config; #define identify_chip2(asic, chipname) \ @@ -410,14 +445,22 @@ bool ac_query_gpu_info(int fd, void *dev_p, else info->max_alloc_size = info->gart_size * 0.7; + info->vram_type = amdinfo->vram_type; + info->vram_bit_width = amdinfo->vram_bit_width; + info->ce_ram_size = amdinfo->ce_ram_size; + + info->l2_cache_size = get_l2_cache_size(info->family); + info->l1_cache_size = 16384; + /* Set which chips have uncached device memory. */ info->has_l2_uncached = info->chip_class >= GFX9; /* Set hardware information. */ info->gds_size = gds.gds_total_size; info->gds_gfx_partition_size = gds.gds_gfx_partition_size; - /* convert the shader clock from KHz to MHz */ + /* convert the shader/memory clocks from KHz to MHz */ info->max_shader_clock = amdinfo->max_engine_clk / 1000; + info->max_memory_clock = amdinfo->max_memory_clk / 1000; info->num_tcc_blocks = device_info.num_tcc_blocks; info->max_se = amdinfo->num_shader_engines; info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine; @@ -502,6 +545,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, * LDS is 128KB in WGP mode and 64KB in CU mode. Assume the WGP mode is used. */ info->lds_size_per_cu = info->chip_class >= GFX10 ? 128 * 1024 : 64 * 1024; + info->lds_granularity = info->chip_class >= GFX7 ? 128 * 4 : 64 * 4; assert(util_is_power_of_two_or_zero(dma.available_rings + 1)); assert(util_is_power_of_two_or_zero(compute.available_rings + 1)); @@ -732,6 +776,7 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" marketing_name = %s\n", info->marketing_name); printf(" is_pro_graphics = %u\n", info->is_pro_graphics); printf(" pci_id = 0x%x\n", info->pci_id); + printf(" pci_rev_id = 0x%x\n", info->pci_rev_id); printf(" family = %i\n", info->family); printf(" chip_class = %i\n", info->chip_class); printf(" family_id = %i\n", info->family_id); @@ -772,6 +817,8 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024)); printf(" vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024)); printf(" vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024)); + printf(" vram_type = %i\n", info->vram_type); + printf(" vram_bit_width = %i\n", info->vram_bit_width); printf(" gds_size = %u kB\n", info->gds_size / 1024); printf(" gds_gfx_partition_size = %u kB\n", info->gds_gfx_partition_size / 1024); printf(" max_alloc_size = %i MB\n", @@ -785,6 +832,11 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" tcc_harvested = %u\n", info->tcc_harvested); printf(" pc_lines = %u\n", info->pc_lines); printf(" lds_size_per_cu = %u\n", info->lds_size_per_cu); + printf(" lds_granularity = %i\n", info->lds_granularity); + printf(" max_memory_clock = %i\n", info->max_memory_clock); + printf(" ce_ram_size = %i\n", info->ce_ram_size); + printf(" l1_cache_size = %i\n", info->l1_cache_size); + printf(" l2_cache_size = %i\n", info->l2_cache_size); printf("CP info:\n"); printf(" gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 41ecb9603eb..fc961bbcd0d 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -49,6 +49,7 @@ struct radeon_info { const char *marketing_name; bool is_pro_graphics; uint32_t pci_id; + uint32_t pci_rev_id; enum radeon_family family; enum chip_class chip_class; uint32_t family_id; @@ -84,6 +85,8 @@ struct radeon_info { uint64_t gart_size; uint64_t vram_size; uint64_t vram_vis_size; + uint32_t vram_bit_width; + uint32_t vram_type; unsigned gds_size; unsigned gds_gfx_partition_size; uint64_t max_alloc_size; @@ -98,6 +101,11 @@ struct radeon_info { bool tcc_harvested; unsigned pc_lines; uint32_t lds_size_per_cu; + uint32_t lds_granularity; + uint32_t max_memory_clock; + uint32_t ce_ram_size; + uint32_t l1_cache_size; + uint32_t l2_cache_size; /* CP info. */ bool gfx_ib_pad_with_type2; -- 2.30.2