From 3de7889d08d0b02f1af6b9027b6e753eb0f6f490 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 12:48:27 +0200
Subject: [PATCH] Separate check for ff's types

---
 tests/efinix/adffs.v  | 40 -------------------------------
 tests/efinix/adffs.ys | 55 +++++++++++++++++++++++++++++++++++++------
 2 files changed, 48 insertions(+), 47 deletions(-)

diff --git a/tests/efinix/adffs.v b/tests/efinix/adffs.v
index 05e68caf7..223b52d21 100644
--- a/tests/efinix/adffs.v
+++ b/tests/efinix/adffs.v
@@ -45,43 +45,3 @@ module ndffnr
 		else
             q <= d;
 endmodule
-
-module top (
-input clk,
-input clr,
-input pre,
-input a,
-output b,b1,b2,b3
-);
-
-dffs u_dffs (
-        .clk (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b )
-    );
-
-ndffnr u_ndffnr (
-        .clk (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b1 )
-    );
-
-adff u_adff (
-        .clk (clk ),
-        .clr (clr),
-        .d (a ),
-        .q (b2 )
-    );
-
-adffn u_adffn (
-        .clk (clk ),
-        .clr (clr),
-        .d (a ),
-        .q (b3 )
-    );
-
-endmodule
diff --git a/tests/efinix/adffs.ys b/tests/efinix/adffs.ys
index 642faa76b..d0be205d5 100644
--- a/tests/efinix/adffs.ys
+++ b/tests/efinix/adffs.ys
@@ -1,12 +1,53 @@
 read_verilog adffs.v
+design -save read
+
 proc
-#async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock
-flatten
-equiv_opt -multiclock -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+hierarchy -top adff
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd adff # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_FF
+select -assert-count 1 t:EFX_GBUFCE
+
+select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
 
+
+design -load read
+proc
+hierarchy -top adffn
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adffn # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_FF
 select -assert-count 1 t:EFX_GBUFCE
-select -assert-count 4 t:EFX_FF
-select -assert-count 2 t:EFX_LUT4
-select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D
+
+select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
+
+
+design -load read
+proc
+hierarchy -top dffs
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_FF
+select -assert-count 1 t:EFX_GBUFCE
+select -assert-count 1 t:EFX_LUT4
+
+select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
+
+
+design -load read
+proc
+hierarchy -top ndffnr
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_FF
+select -assert-count 1 t:EFX_GBUFCE
+
+select -assert-count 1 t:EFX_FF
+select -assert-count 1 t:EFX_GBUFCE
+select -assert-count 1 t:EFX_LUT4
+
+select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
-- 
2.30.2