From 3deff78fe40b9aa3d4e3a8571f13f29072efe4e4 Mon Sep 17 00:00:00 2001 From: Nikos Nikoleris Date: Wed, 13 Sep 2017 12:23:25 +0100 Subject: [PATCH] mem: Ignore clean requests in the abstract memory Systems with atomic cores and the fastmem option enabled bypass the whole memory system and access the abstract memory directly. Cache maintenance operations which would be normally handled before the point of unification/coherence should be ignored by the abstract memory. Change-Id: I696cdd158222e5fd67f670cddbcf2efbbfd5eca4 Reviewed-by: Curtis Dunham Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/5054 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- src/mem/abstract_mem.cc | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc index 13a0873cb..b41c82b0d 100644 --- a/src/mem/abstract_mem.cc +++ b/src/mem/abstract_mem.cc @@ -399,13 +399,12 @@ AbstractMemory::access(PacketPtr pkt) bytesRead[pkt->req->masterId()] += pkt->getSize(); if (pkt->req->isInstFetch()) bytesInstRead[pkt->req->masterId()] += pkt->getSize(); - } else if (pkt->isInvalidate()) { + } else if (pkt->isInvalidate() || pkt->isClean()) { + assert(!pkt->isWrite()); + // in a fastmem system invalidating and/or cleaning packets + // can be seen due to cache maintenance requests + // no need to do anything - // this clause is intentionally before the write clause: the only - // transaction that is both a write and an invalidate is - // WriteInvalidate, and for the sake of consistency, it does not - // write to memory. in a cacheless system, there are no WriteInv's - // because the Write -> WriteInvalidate rewrite happens in the cache. } else if (pkt->isWrite()) { if (writeOK(pkt)) { if (pmemAddr) { @@ -419,7 +418,7 @@ AbstractMemory::access(PacketPtr pkt) bytesWritten[pkt->req->masterId()] += pkt->getSize(); } } else { - panic("unimplemented"); + panic("Unexpected packet %s", pkt->print()); } if (pkt->needsResponse()) { -- 2.30.2