From 3df3a316d3da8dcfff021182d762e20af4379df2 Mon Sep 17 00:00:00 2001 From: Michael Snyder Date: Thu, 19 Jun 2003 02:40:12 +0000 Subject: [PATCH] 2003-05-30 Alexandre Oliva * allinsn.exp: Fix typos introduced on 2003-05-27. 2003-05-29 Michael Snyder * tas.s: Use er4 for h8h and h8s, er3 for h8sx. 2003-05-28 Michael Snyder * subs.s: New file. * subx.s: New file. * allinsn.exp: Add new subs and subx tests. * testutils.inc: Simplify (and fix) set_carry_flag. (clear_carry_flag, set_zero_flag, clear_zero_flag...): New macros. * addx.s: Use simplified set_carry_flag. 2003-05-27 Michael Snyder * tas.s: New file. * band.s: New file. * biand.s: New file. * allinsn.exp: Add tas, band, biand tests. * brabc.s: Add abs8 test. * bset.s: Add bset/ne, bclr/ne tests. 2003-05-23 Michael Snyder * and.b.s: Add andc exr. * or.b.s: Add orc.exr. * xor.b.s: Add xor exr. * jmp.s: Fix 8-bit indirect test. Add 7-bit vector test. 2003-05-22 Michael Snyder * stack.s: Add rte/l and rts/l tests. * allinsn.exp: Add stack tests. 2003-05-21 Michael Snyder * stack.s: New file: test stack operations. * stack.s: Add bsr, jsr tests. * stack.s: Add trapa, rte tests. * div.s: Corrections for size of dividend. 2003-05-20 Michael Snyder * mul.s: Corrections for unsigned multiply. * div.s: New file, test div instructions. * allinsn.exp: Add div test. 2003-05-19 Michael Snyder * mul.s: New file, test mul instructions. * allinsn.exp: Add mul test. --- sim/testsuite/sim/h8300/ChangeLog | 59 ++ sim/testsuite/sim/h8300/addx.s | 13 +- sim/testsuite/sim/h8300/allinsn.exp | 55 +- sim/testsuite/sim/h8300/andb.s | 42 +- sim/testsuite/sim/h8300/band.s | 525 +++++++++++++ sim/testsuite/sim/h8300/biand.s | 473 ++++++++++++ sim/testsuite/sim/h8300/brabc.s | 45 +- sim/testsuite/sim/h8300/bset.s | 53 +- sim/testsuite/sim/h8300/div.s | 387 ++++++++++ sim/testsuite/sim/h8300/jmp.s | 36 +- sim/testsuite/sim/h8300/ldm.s | 5 +- sim/testsuite/sim/h8300/mac.s | 2 +- sim/testsuite/sim/h8300/mul.s | 474 ++++++++++++ sim/testsuite/sim/h8300/orb.s | 41 +- sim/testsuite/sim/h8300/stack.s | 445 +++++++++++ sim/testsuite/sim/h8300/subs.s | 74 ++ sim/testsuite/sim/h8300/subx.s | 1010 +++++++++++++++++++++++++ sim/testsuite/sim/h8300/tas.s | 80 ++ sim/testsuite/sim/h8300/testutils.inc | 46 +- sim/testsuite/sim/h8300/xorb.s | 53 +- 20 files changed, 3830 insertions(+), 88 deletions(-) create mode 100644 sim/testsuite/sim/h8300/band.s create mode 100644 sim/testsuite/sim/h8300/biand.s create mode 100644 sim/testsuite/sim/h8300/div.s create mode 100644 sim/testsuite/sim/h8300/mul.s create mode 100644 sim/testsuite/sim/h8300/stack.s create mode 100644 sim/testsuite/sim/h8300/subs.s create mode 100644 sim/testsuite/sim/h8300/subx.s create mode 100644 sim/testsuite/sim/h8300/tas.s diff --git a/sim/testsuite/sim/h8300/ChangeLog b/sim/testsuite/sim/h8300/ChangeLog index e03bb3c283e..3f1c1d31260 100644 --- a/sim/testsuite/sim/h8300/ChangeLog +++ b/sim/testsuite/sim/h8300/ChangeLog @@ -1,3 +1,62 @@ +2003-05-30 Alexandre Oliva + + * allinsn.exp: Fix typos introduced on 2003-05-27. + +2003-05-29 Michael Snyder + + * tas.s: Use er4 for h8h and h8s, er3 for h8sx. + +2003-05-28 Michael Snyder + + * subs.s: New file. + * subx.s: New file. + * allinsn.exp: Add new subs and subx tests. + * testutils.inc: Simplify (and fix) set_carry_flag. + (clear_carry_flag, set_zero_flag, clear_zero_flag...): New macros. + * addx.s: Use simplified set_carry_flag. + +2003-05-27 Michael Snyder + + * tas.s: New file. + * band.s: New file. + * biand.s: New file. + * allinsn.exp: Add tas, band, biand tests. + * brabc.s: Add abs8 test. + * bset.s: Add bset/ne, bclr/ne tests. + +2003-05-23 Michael Snyder + + * and.b.s: Add andc exr. + * or.b.s: Add orc.exr. + * xor.b.s: Add xor exr. + + * jmp.s: Fix 8-bit indirect test. Add 7-bit vector test. + +2003-05-22 Michael Snyder + + * stack.s: Add rte/l and rts/l tests. + * allinsn.exp: Add stack tests. + +2003-05-21 Michael Snyder + + * stack.s: New file: test stack operations. + * stack.s: Add bsr, jsr tests. + * stack.s: Add trapa, rte tests. + + * div.s: Corrections for size of dividend. + +2003-05-20 Michael Snyder + + * mul.s: Corrections for unsigned multiply. + + * div.s: New file, test div instructions. + * allinsn.exp: Add div test. + +2003-05-19 Michael Snyder + + * mul.s: New file, test mul instructions. + * allinsn.exp: Add mul test. + 2003-05-14 Michael Snyder * addb.s, addw.s, addl.s, addw.s, addx.s, andb.s, andw.s, andl.s, diff --git a/sim/testsuite/sim/h8300/addx.s b/sim/testsuite/sim/h8300/addx.s index 27697a7e4d5..ef4e9d3b5cd 100644 --- a/sim/testsuite/sim/h8300/addx.s +++ b/sim/testsuite/sim/h8300/addx.s @@ -22,7 +22,6 @@ # addx.b @ers, @erd ; 0 1 7 4 6 8 ers d 0 erd 1 ???? # addx.b @ers-, @erd- ; 0 1 7 6 6 c ers d a erd 1 ???? # - # coming soon: # word ops # long ops @@ -70,7 +69,7 @@ addx_b_imm8_1: set_ccr_zero ;; addx.b #xx:8,Rd ; Addx with carry initially one. - set_carry_flag 1 + set_carry_flag addx.b #5, r0l ; Immediate 8-bit operand test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 @@ -181,7 +180,7 @@ addx_b_reg8_1: ;; addx.b Rs,Rd ; addx with carry initially one mov.b #5, r0h - set_carry_flag 1 + set_carry_flag addx.b r0h, r0l ; Register operand test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 @@ -393,7 +392,7 @@ addx_w_imm16_1: set_ccr_zero ;; addx.w #xx:16,Rd ; Addx with carry initially one. - set_carry_flag 1 + set_carry_flag addx.w #0x505, r0 ; Immediate 16-bit operand test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 @@ -497,7 +496,7 @@ addx_w_reg16_1: ;; addx.w Rs,Rd ; addx with carry initially one mov.w #0x505, e0 - set_carry_flag 1 + set_carry_flag addx.w e0, r0 ; Register operand test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 @@ -704,7 +703,7 @@ addx_l_imm32_1: set_ccr_zero ;; addx.l #xx:32,Rd ; Addx with carry initially one. - set_carry_flag 1 + set_carry_flag addx.l #0x50505, er0 ; Immediate 32-bit operand test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 @@ -807,7 +806,7 @@ addx_l_reg32_1: ;; addx.l Rs,Rd ; addx with carry initially one mov.l #0x50505, er0 - set_carry_flag 1 + set_carry_flag addx.l er0, er1 ; Register operand test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 diff --git a/sim/testsuite/sim/h8300/allinsn.exp b/sim/testsuite/sim/h8300/allinsn.exp index 9f3351bbc79..82fedebe211 100644 --- a/sim/testsuite/sim/h8300/allinsn.exp +++ b/sim/testsuite/sim/h8300/allinsn.exp @@ -3,43 +3,46 @@ set all "h8300 h8300h h8300s h8sx" if {[istarget h8300*-*-*] || [istarget h8sx*-*-*]} then { - run_sim_test addb.s $all - run_sim_test addw.s $all - run_sim_test addl.s $all + run_sim_test addb.s $all + run_sim_test addw.s $all + run_sim_test addl.s $all run_sim_test adds.s $all run_sim_test addx.s $all - run_sim_test andb.s $all - run_sim_test andw.s $all - run_sim_test andl.s $all + run_sim_test andb.s $all + run_sim_test andw.s $all + run_sim_test andl.s $all + run_sim_test band.s $all run_sim_test bfld.s h8sx - run_sim_test brabc.s h8sx + run_sim_test biand.s $all run_sim_test bra.s $all run_sim_test bset.s $all - run_sim_test cmpb.s $all - run_sim_test cmpw.s $all - run_sim_test cmpl.s $all + run_sim_test cmpb.s $all + run_sim_test cmpw.s $all + run_sim_test cmpl.s $all run_sim_test daa.s $all run_sim_test das.s $all run_sim_test dec.s $all - run_sim_test extw.s $all - run_sim_test extl.s $all + run_sim_test div.s $all + run_sim_test extw.s $all + run_sim_test extl.s $all run_sim_test inc.s $all run_sim_test jmp.s $all run_sim_test ldc.s $all run_sim_test ldm.s $all run_sim_test mac.s $all + run_sim_test movb.s $all + run_sim_test movw.s $all + run_sim_test movl.s $all run_sim_test mova.s h8sx - run_sim_test movb.s $all - run_sim_test movw.s $all - run_sim_test movl.s $all run_sim_test movmd.s h8sx run_sim_test movsd.s h8sx + run_sim_test mul.s $all run_sim_test neg.s $all run_sim_test nop.s $all run_sim_test not.s $all - run_sim_test orb.s $all - run_sim_test orw.s $all - run_sim_test orl.s $all + run_sim_test orb.s $all + run_sim_test orw.s $all + run_sim_test orl.s $all run_sim_test rotl.s $all run_sim_test rotr.s $all run_sim_test rotxl.s $all @@ -48,11 +51,15 @@ if {[istarget h8300*-*-*] || [istarget h8sx*-*-*]} then { run_sim_test shar.s $all run_sim_test shll.s $all run_sim_test shlr.s $all + run_sim_test stack.s $all run_sim_test stc.s $all - run_sim_test subb.s $all - run_sim_test subw.s $all - run_sim_test subl.s $all - run_sim_test xorb.s $all - run_sim_test xorw.s $all - run_sim_test xorl.s $all + run_sim_test subb.s $all + run_sim_test subw.s $all + run_sim_test subl.s $all + run_sim_test subs.s $all + run_sim_test subx.s $all + run_sim_test tas.s $all + run_sim_test xorb.s $all + run_sim_test xorw.s $all + run_sim_test xorl.s $all } diff --git a/sim/testsuite/sim/h8300/andb.s b/sim/testsuite/sim/h8300/andb.s index 33776748a7d..8f11805517d 100644 --- a/sim/testsuite/sim/h8300/andb.s +++ b/sim/testsuite/sim/h8300/andb.s @@ -238,8 +238,7 @@ and_b_imm8_rdpredec: fail .L5: - -.endif +.endif ; h8sx and_b_reg8_reg8: set_grs_a5a5 ; Fill all general regs with a fixed pattern @@ -452,6 +451,7 @@ and_b_reg8_rdpredec: beq .L10 fail .L10: +.endif ; h8sx andc_imm8_ccr: set_grs_a5a5 ; Fill all general regs with a fixed pattern @@ -484,8 +484,44 @@ andc_imm8_ccr: test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 + +.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr +andc_imm8_exr: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ldc #0xff, exr + stc exr, r0l + test_h_gr8 0x87, r0l + + ;; andc #xx:8,exr + set_ccr_zero + andc #0x7f, exr + test_cc_clear + stc exr, r0l + test_h_gr8 0x7, r0l + + andc #0x3, exr + stc exr, r0l + test_h_gr8 0x3, r0l + + andc #0x1, exr + stc exr, r0l + test_h_gr8 0x1, r0l + + andc #0x0, exr + stc exr, r0l + test_h_gr8 0x0, r0l + + test_h_gr32 0xa5a5a500 er0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; not h8300 or h8300h -.endif pass exit 0 diff --git a/sim/testsuite/sim/h8300/band.s b/sim/testsuite/sim/h8300/band.s new file mode 100644 index 00000000000..f3455ad4cb8 --- /dev/null +++ b/sim/testsuite/sim/h8300/band.s @@ -0,0 +1,525 @@ +# Hitachi H8 testcase 'band', 'bor', 'bxor', 'bld', 'bst', 'bstz' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +byte_src: .byte 0xa5 +byte_dst: .byte 0 + + start + +band_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; band xx:3, reg8 + band #7, r0l ; this should NOT set the carry flag. + test_cc_clear + band #6, r0l ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + band #7, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + band #6, r0l ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +band_imm3_ind: + set_grs_a5a5 +.if (sim_cpu == h8300) + mov #byte_src, r1 + set_ccr_zero + ;; band xx:3, ind + band #7, @r1 ; this should NOT set the carry flag. + test_cc_clear + band #6, @r1 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + band #7, @r1 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + band #6, @r1 ; this should clear the carry flag + test_cc_clear +;;; test_h_gr16 byte_src r1 ;FIXME +.else + mov #byte_src, er1 + set_ccr_zero + ;; band xx:3, ind + band #7, @er1 ; this should NOT set the carry flag. + test_cc_clear + band #6, @er1 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + band #7, @er1 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + band #6, @er1 ; this should clear the carry flag + test_cc_clear + test_h_gr32 byte_src er1 +.endif ; h8300 + test_gr_a5a5 0 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +band_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; band xx:3, aa:8 + band #7, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + band #6, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + band #7, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + band #6, @0x20:8 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +.if (sim_cpu) ; non-zero means not h8300 +band_imm3_abs16: + set_grs_a5a5 + set_ccr_zero + ;; band xx:3, aa:16 + band #7, @byte_src:16 ; this should NOT set the carry flag. + test_cc_clear + band #6, @byte_src:16 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + band #7, @byte_src:16 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + band #6, @byte_src:16 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +band_imm3_abs32: + set_grs_a5a5 + set_ccr_zero + ;; band xx:3, aa:32 + band #7, @byte_src:32 ; this should NOT set the carry flag. + test_cc_clear + band #6, @byte_src:32 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + band #7, @byte_src:32 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + band #6, @byte_src:32 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. +.endif + +bor_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bor xx:3, reg8 + bor #6, r0l ; this should NOT set the carry flag. + test_cc_clear + + bor #7, r0l ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bor #7, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + bor #6, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bor_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bor xx:3, aa:8 + bor #6, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + bor #7, @0x20:8 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bor #7, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + bor #6, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bxor_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bxor xx:3, reg8 + bxor #6, r0l ; this should NOT set the carry flag. + test_cc_clear + + bxor #7, r0l ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bxor #6, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + bxor #7, r0l ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +bxor_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bxor xx:3, aa:8 + bxor #6, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + bxor #7, @0x20:8 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bxor #6, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + bxor #7, @0x20:8 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +bld_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bld xx:3, reg8 + bld #6, r0l ; this should NOT set the carry flag. + test_cc_clear + bld #7, r0l ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bld_imm3_ind: + set_grs_a5a5 +.if (sim_cpu == h8300) + mov #byte_src, r1 + set_ccr_zero + ;; bld xx:3, ind + bld #6, @r1 ; this should NOT set the carry flag. + test_cc_clear + bld #7, @r1 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear +;;; test_h_gr16 byte_src r1 ;FIXME +.else + mov #byte_src, er1 + set_ccr_zero + ;; bld xx:3, ind + bld #6, @er1 ; this should NOT set the carry flag. + test_cc_clear + bld #7, @er1 ; this should NOT set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + test_h_gr32 byte_src er1 +.endif ; h8300 + test_gr_a5a5 0 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bld_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bld xx:3, aa:8 + bld #6, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + bld #7, @0x20:8 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +.if (sim_cpu) ; non-zero means not h8300 +bld_imm3_abs16: + set_grs_a5a5 + set_ccr_zero + ;; bld xx:3, aa:16 + bld #6, @byte_src:16 ; this should NOT set the carry flag. + test_cc_clear + bld #7, @byte_src:16 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bld_imm3_abs32: + set_grs_a5a5 + set_ccr_zero + ;; bld xx:3, aa:32 + bld #6, @byte_src:32 ; this should NOT set the carry flag. + test_cc_clear + bld #7, @byte_src:32 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. +.endif + +bst_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bst xx:3, reg8 + bst #7, r0l ; this should clear bit 7 + test_cc_clear + test_h_gr16 0xa525 r0 + + set_ccr_zero + orc #1, ccr ; set the carry flag + bst #6, r0l ; this should set bit 6 + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + test_h_gr16 0xa565 r0 + + test_gr_a5a5 1 ; Rest of general regs should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bst_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bst xx:3, aa:8 + bst #7, @0x20:8 ; this should clear bit 7 + test_cc_clear + mov.b @0x20, r0l + test_h_gr16 0xa525 r0 + + set_ccr_zero + orc #1, ccr ; set the carry flag + bst #6, @0x20:8 ; this should set bit 6 + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + mov.b @0x20, r0l + test_h_gr16 0xa565 r0 + + test_gr_a5a5 1 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +bstz_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bstz xx:3, aa:8 + bstz #7, @0x20:8 ; this should clear bit 7 + test_cc_clear + mov.b @0x20, r0l + test_h_gr16 0xa525 r0 + + set_ccr_zero + orc #4, ccr ; set the zero flag + bstz #6, @0x20:8 ; this should set bit 6 + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set + mov.b @0x20, r0l + test_h_gr16 0xa565 r0 + + test_gr_a5a5 1 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + +btst_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; btst xx:3, reg8 + btst #7, r0l ; this should NOT set the zero flag. + test_cc_clear + btst #6, r0l ; this should set the zero flag. + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set + + test_grs_a5a5 ; general registers should not be changed. + +btst_imm3_ind: + set_grs_a5a5 +.if (sim_cpu == h8300) + mov #byte_src, r1 + set_ccr_zero + ;; btst xx:3, ind + btst #7, @r1 ; this should NOT set the zero flag. + test_cc_clear + btst #6, @r1 ; this should set the zero flag. + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set +;;; test_h_gr16 byte_src r1 ;FIXME +.else + mov #byte_src, er1 + set_ccr_zero + ;; btst xx:3, ind + btst #7, @er1 ; this should NOT set the zero flag. + test_cc_clear + btst #6, @er1 ; this should NOT set the zero flag. + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set + test_h_gr32 byte_src er1 +.endif ; h8300 + test_gr_a5a5 0 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +btst_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; btst xx:3, aa:8 + btst #7, @0x20:8 ; this should NOT set the zero flag. + test_cc_clear + btst #6, @0x20:8 ; this should set the zero flag. + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set + + test_grs_a5a5 ; general registers should not be changed. + +.if (sim_cpu) ; non-zero means not h8300 +btst_imm3_abs16: + set_grs_a5a5 + set_ccr_zero + ;; btst xx:3, aa:16 + btst #7, @byte_src:16 ; this should NOT set the zero flag. + test_cc_clear + btst #6, @byte_src:16 ; this should set the zero flag. + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set + + test_grs_a5a5 ; general registers should not be changed. + +btst_imm3_abs32: + set_grs_a5a5 + set_ccr_zero + ;; btst xx:3, aa:32 + btst #7, @byte_src:32 ; this should NOT set the zero flag. + test_cc_clear + btst #6, @byte_src:32 ; this should set the zero flag. + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set + + test_grs_a5a5 ; general registers should not be changed. +.endif + + pass + exit 0 diff --git a/sim/testsuite/sim/h8300/biand.s b/sim/testsuite/sim/h8300/biand.s new file mode 100644 index 00000000000..07d3ecfe044 --- /dev/null +++ b/sim/testsuite/sim/h8300/biand.s @@ -0,0 +1,473 @@ +# Hitachi H8 testcase 'biand', 'bior', 'bixor', 'bild', 'bist', 'bistz' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +byte_src: .byte 0xa5 +byte_dst: .byte 0 + + start + +biand_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; biand xx:3, reg8 + biand #6, r0l ; this should NOT set the carry flag. + test_cc_clear + biand #7, r0l ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + biand #6, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + biand #7, r0l ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +biand_imm3_ind: + set_grs_a5a5 +.if (sim_cpu == h8300) + mov #byte_src, r1 + set_ccr_zero + ;; biand xx:3, ind + biand #6, @r1 ; this should NOT set the carry flag. + test_cc_clear + biand #7, @r1 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + biand #6, @r1 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + biand #7, @r1 ; this should clear the carry flag + test_cc_clear +;;; test_h_gr16 byte_src r1 ;FIXME +.else + mov #byte_src, er1 + set_ccr_zero + ;; biand xx:3, ind + biand #6, @er1 ; this should NOT set the carry flag. + test_cc_clear + biand #7, @er1 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + biand #6, @er1 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + biand #7, @er1 ; this should clear the carry flag + test_cc_clear + test_h_gr32 byte_src er1 +.endif ; h8300 + test_gr_a5a5 0 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +biand_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; biand xx:3, aa:8 + biand #6, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + biand #7, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + biand #6, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + biand #7, @0x20:8 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +.if (sim_cpu) ; non-zero means not h8300 +biand_imm3_abs16: + set_grs_a5a5 + set_ccr_zero + ;; biand xx:3, aa:16 + biand #6, @byte_src:16 ; this should NOT set the carry flag. + test_cc_clear + biand #7, @byte_src:16 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + biand #6, @byte_src:16 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + biand #7, @byte_src:16 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +biand_imm3_abs32: + set_grs_a5a5 + set_ccr_zero + ;; biand xx:3, aa:32 + biand #6, @byte_src:32 ; this should NOT set the carry flag. + test_cc_clear + biand #7, @byte_src:32 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + biand #6, @byte_src:32 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + biand #7, @byte_src:32 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. +.endif + +bior_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bior xx:3, reg8 + bior #7, r0l ; this should NOT set the carry flag. + test_cc_clear + + bior #6, r0l ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bior #6, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + bior #7, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bior_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bior xx:3, aa:8 + bior #7, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + bior #6, @0x20:8 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bior #6, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + bior #7, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bixor_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bixor xx:3, reg8 + bixor #7, r0l ; this should NOT set the carry flag. + test_cc_clear + + bixor #6, r0l ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bixor #7, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + bixor #6, r0l ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +bixor_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bixor xx:3, aa:8 + bixor #7, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + bixor #6, @0x20:8 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bixor #7, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + bixor #6, @0x20:8 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +bild_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bild xx:3, reg8 + bild #7, r0l ; this should NOT set the carry flag. + test_cc_clear + bild #6, r0l ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bild_imm3_ind: + set_grs_a5a5 +.if (sim_cpu == h8300) + mov #byte_src, r1 + set_ccr_zero + ;; bild xx:3, ind + bild #7, @r1 ; this should NOT set the carry flag. + test_cc_clear + bild #6, @r1 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear +;;; test_h_gr16 byte_src r1 ;FIXME +.else + mov #byte_src, er1 + set_ccr_zero + ;; bild xx:3, ind + bild #7, @er1 ; this should NOT set the carry flag. + test_cc_clear + bild #6, @er1 ; this should NOT set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + test_h_gr32 byte_src er1 +.endif ; h8300 + test_gr_a5a5 0 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bild_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bild xx:3, aa:8 + bild #7, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + bild #6, @0x20:8 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +.if (sim_cpu) ; non-zero means not h8300 +bild_imm3_abs16: + set_grs_a5a5 + set_ccr_zero + ;; bild xx:3, aa:16 + bild #7, @byte_src:16 ; this should NOT set the carry flag. + test_cc_clear + bild #6, @byte_src:16 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bild_imm3_abs32: + set_grs_a5a5 + set_ccr_zero + ;; bild xx:3, aa:32 + bild #7, @byte_src:32 ; this should NOT set the carry flag. + test_cc_clear + bild #6, @byte_src:32 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. +.endif + +bist_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bist xx:3, reg8 + bist #6, r0l ; this should set bit 6 + test_cc_clear + test_h_gr16 0xa5e5 r0 + + set_ccr_zero + orc #1, ccr ; set the carry flag + bist #7, r0l ; this should clear bit 7 + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + test_h_gr16 0xa565 r0 + + test_gr_a5a5 1 ; Rest of general regs should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bist_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bist xx:3, aa:8 + bist #6, @0x20:8 ; this should set bit 6 + test_cc_clear + mov.b @0x20, r0l + test_h_gr16 0xa5e5 r0 + + set_ccr_zero + orc #1, ccr ; set the carry flag + bist #7, @0x20:8 ; this should clear bit 7 + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + mov.b @0x20, r0l + test_h_gr16 0xa565 r0 + + test_gr_a5a5 1 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +bistz_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bistz xx:3, aa:8 + bistz #6, @0x20:8 ; this should set bit 6 + test_cc_clear + mov.b @0x20, r0l + test_h_gr16 0xa5e5 r0 + + set_ccr_zero + orc #4, ccr ; set the zero flag + bistz #7, @0x20:8 ; this should clear bit 7 + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set + mov.b @0x20, r0l + test_h_gr16 0xa565 r0 + + test_gr_a5a5 1 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + +bnot_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bnot xx:3, reg8 + bnot #7, r0l + test_cc_clear + test_h_gr16 0xa525 r0 + set_ccr_zero + bnot #6, r0l + test_cc_clear + test_h_gr16 0xa565 r0 + set_ccr_zero + bnot #5, r0l + test_cc_clear + test_h_gr16 0xa545 r0 + set_ccr_zero + bnot #4, r0l + test_cc_clear + test_h_gr16 0xa555 r0 + set_ccr_zero + + bnot #4, r0l + bnot #5, r0l + bnot #6, r0l + bnot #7, r0l + test_cc_clear + test_grs_a5a5 ; general registers should not be changed. + +bnot_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bnot xx:3, aa:8 + bnot #7, @0x20:8 + bnot #6, @0x20:8 + bnot #5, @0x20:8 + bnot #4, @0x20:8 + test_cc_clear + test_grs_a5a5 + mov @0x20, r0l + test_h_gr16 0xa555 r0 + + pass + exit 0 diff --git a/sim/testsuite/sim/h8300/brabc.s b/sim/testsuite/sim/h8300/brabc.s index 119d8d9cac8..b9a08ea02ef 100644 --- a/sim/testsuite/sim/h8300/brabc.s +++ b/sim/testsuite/sim/h8300/brabc.s @@ -43,18 +43,28 @@ brabc_ind_disp8: test_h_gr32 0xa5a5a5a5 er6 test_h_gr32 0xa5a5a5a5 er7 -brabc_abs16_disp16: +brabc_abs8_disp16: set_grs_a5a5 + mov.b #0xa5, @0x20:32 set_ccr_zero - ;; bra/bc xx:3, @aa:16, disp16 - bra/bc #1, @byte_src:16, .Lpass3:16 + ;; bra/bc xx:3, @aa:8, disp16 + bra/bc #1, @0x20:8, .Lpass3:16 fail .Lpass3: - bra/bc #2, @byte_src:16, .Lfail2:16 - bra .Lpass4 -.Lfail2: + bra/bc #2, @0x20:8, Lfail:16 + + test_cc_clear + test_grs_a5a5 + +brabc_abs16_disp16: + set_grs_a5a5 + set_ccr_zero + ;; bra/bc xx:3, @aa:16, disp16 + bra/bc #1, @byte_src:16, .Lpass5:16 fail -.Lpass4: +.Lpass5: + bra/bc #2, @byte_src:16, Lfail:16 + test_cc_clear test_grs_a5a5 @@ -63,18 +73,18 @@ brabs_ind_disp8: mov #byte_src, er1 set_ccr_zero ;; bra/bs xx:3, @erd, disp8 - bra/bs #2, @er1, .Lpass5:8 + bra/bs #2, @er1, .Lpass7:8 ;;; .word 0x7c10 ;;; .word 0x4a10 fail -.Lpass5: +.Lpass7: bra/bs #1, @er1, .Lfail3:8 ;;; .word 0x7c10 ;;; .word 0x4902 - bra .Lpass6 + bra .Lpass8 .Lfail3: fail -.Lpass6: +.Lpass8: test_cc_clear test_h_gr32 0xa5a5a5a5 er0 test_h_gr32 byte_src er1 @@ -89,14 +99,11 @@ brabs_abs32_disp16: set_grs_a5a5 set_ccr_zero ;; bra/bs xx:3, @aa:32, disp16 - bra/bs #2, @byte_src:32, .Lpass7:16 + bra/bs #2, @byte_src:32, .Lpass9:16 fail -.Lpass7: - bra/bs #1, @byte_src:32, .Lfail4:16 - bra .Lpass8 -.Lfail4: - fail -.Lpass8: +.Lpass9: + bra/bs #1, @byte_src:32, Lfail:16 + test_cc_clear test_grs_a5a5 @@ -105,3 +112,5 @@ brabs_abs32_disp16: pass exit 0 + +Lfail: fail diff --git a/sim/testsuite/sim/h8300/bset.s b/sim/testsuite/sim/h8300/bset.s index ecf52373bf8..a94e916b26c 100644 --- a/sim/testsuite/sim/h8300/bset.s +++ b/sim/testsuite/sim/h8300/bset.s @@ -824,11 +824,56 @@ bclr_eq_imm3_abs32: test_h_gr8 0 r1l test_gr_a5a5 0 ; Make sure other general regs not disturbed -.if (sim_cpu == h8300) - test_h_gr16 0xa500 r1 -.else test_h_gr32 0xa5a5a500 er1 -.endif + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bset_ne_imm3_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; bset/ne xx:3, aa:16 + mov #0, @byte_dst + set_ccr_zero + orc #4, ccr ; Set zero flag + bset/ne #0, @byte_dst:16 ; Zero is set; should have no effect. + test_zero_set + test_neg_clear + test_ovf_clear + test_carry_clear + mov @byte_dst, r1l + test_h_gr8 0 r1l + + set_ccr_zero + bset/ne #0, @byte_dst:16 ; Zero is clear: operation should succeed. + test_cc_clear + mov @byte_dst, r1l + test_h_gr8 1 r1l + +bclr_ne_imm3_abs32: + mov #1, @byte_dst + set_ccr_zero + orc #4, ccr ; Set zero flag + ;; bclr/ne xx:3, aa:16 + bclr/ne #0, @byte_dst:32 ; Zero is set, should have no effect. + test_neg_clear + test_zero_set + test_ovf_clear + test_carry_clear + mov @byte_dst, r1l + test_h_gr8 1 r1l + + set_ccr_zero + bclr/ne #0, @byte_dst:32 ; Zero is clear: operation should succeed. + test_cc_clear + mov @byte_dst, r1l + test_h_gr8 0 r1l + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0xa5a5a500 er1 test_gr_a5a5 2 test_gr_a5a5 3 test_gr_a5a5 4 diff --git a/sim/testsuite/sim/h8300/div.s b/sim/testsuite/sim/h8300/div.s new file mode 100644 index 00000000000..518b62f9523 --- /dev/null +++ b/sim/testsuite/sim/h8300/div.s @@ -0,0 +1,387 @@ +# Hitachi H8 testcase 'divs', 'divu', 'divxs', 'divxu' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) +divs_w_reg_reg: + set_grs_a5a5 + + ;; divs.w rs, rd + mov.w #32, r1 + mov.w #-2, r2 + set_ccr_zero + divs.w r2, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 0xfff0 r1 + test_h_gr32 0xa5a5fffe er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +divs_w_imm4_reg: + set_grs_a5a5 + + ;; divs.w xx:4, rd + mov.w #32, r1 + set_ccr_zero + divs.w #-2:4, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 -16 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +divs_l_reg_reg: + set_grs_a5a5 + + ;; divs.l ers, erd + mov.l #320000, er1 + mov.l #-2, er2 + set_ccr_zero + divs.l er2, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 -160000 er1 + test_h_gr32 -2 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +divs_l_imm4_reg: + set_grs_a5a5 + + ;; divs.l xx:4, rd + mov.l #320000, er1 + set_ccr_zero + divs.l #-2:4, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 -160000 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +divu_w_reg_reg: + set_grs_a5a5 + + ;; divu.w rs, rd + mov.w #32, r1 + mov.w #2, r2 + set_ccr_zero + divu.w r2, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 16 r1 + test_h_gr32 0xa5a50002 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +divu_w_imm4_reg: + set_grs_a5a5 + + ;; divu.w xx:4, rd + mov.w #32, r1 + set_ccr_zero + divu.w #2:4, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 16 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +divu_l_reg_reg: + set_grs_a5a5 + + ;; divu.l ers, erd + mov.l #320000, er1 + mov.l #2, er2 + set_ccr_zero + divu.l er2, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 160000 er1 + test_h_gr32 2 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +divu_l_imm4_reg: + set_grs_a5a5 + + ;; divu.l xx:4, rd + mov.l #320000, er1 + set_ccr_zero + divu.l #2:4, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 160000 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + +.if (sim_cpu) ; not equal to zero ie. not h8 +divxs_b_reg_reg: + set_grs_a5a5 + + ;; divxs.b rs, rd + mov.w #32, r1 + mov.b #-2, r2l + set_ccr_zero + divxs.b r2l, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 0x00f0 r1 + test_h_gr32 0xa5a5a5fe er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +divxs_b_imm4_reg: + set_grs_a5a5 + + ;; divxs.b xx:4, rd + mov.w #32, r1 + set_ccr_zero + divxs.b #-2:4, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 0x00f0 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + +divxs_w_reg_reg: + set_grs_a5a5 + + ;; divxs.w ers, erd + mov.l #0x1000, er1 + mov.w #-0x1000, r2 + set_ccr_zero + divxs.w r2, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 0x0000ffff er1 + test_h_gr32 0xa5a5f000 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +divxs_w_imm4_reg: + set_grs_a5a5 + + ;; divxs.w xx:4, rd + mov.l #-4, er1 + set_ccr_zero + divxs.w #2:4, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 0x0000fffe er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx +.endif ; not h8 + +divxu_b_reg_reg: + set_grs_a5a5 + + ;; divxu.b rs, rd + mov.w #32, r1 + mov.b #2, r2l + set_ccr_zero + divxu.b r2l, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 0x0010 r1 + test_h_gr16 0xa502 r2 +.if (sim_cpu) + test_h_gr32 0xa5a5a502 er2 +.endif + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu) ; not h8 +.if (sim_cpu == h8sx) +divxu_b_imm4_reg: + set_grs_a5a5 + + ;; divxu.b xx:4, rd + mov.w #32, r1 + set_ccr_zero + divxu.b #2:4, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 0x0010 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + +divxu_w_reg_reg: + set_grs_a5a5 + + ;; divxu.w ers, erd + mov.l #0x1000, er1 + mov.w #0x1000, r2 + set_ccr_zero + divxu.w r2, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 0x00000001 er1 + test_h_gr32 0xa5a51000 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +divxu_w_imm4_reg: + set_grs_a5a5 + + ;; divxu.w xx:4, rd + mov.l #0xffff, er1 + set_ccr_zero + divxu.w #2:4, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 0x00017fff er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx +.endif ; not h8 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/jmp.s b/sim/testsuite/sim/h8300/jmp.s index 805bafe1ef5..30a4b284caa 100644 --- a/sim/testsuite/sim/h8300/jmp.s +++ b/sim/testsuite/sim/h8300/jmp.s @@ -10,15 +10,19 @@ .include "testutils.inc" + .data +vector_area: + .fill 0x400, 1, 0 + start -.if 0 ; this one isn't right -- it's an indirect +.if (sim_cpu == h8sx) jmp_8: set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #.Ltgt_8:32, @0x20 set_ccr_zero - - ;; jmp @aa:8 ; 8-bit displacement - jmp @@.Ltgt_8:8 + ;; jmp @@aa:8 ; 8-bit displacement + jmp @@0x20 fail .Ltgt_8: @@ -31,7 +35,23 @@ jmp_8: test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 -.endif + +jmp_7: ; vector jump + mov.l #vector_area, er0 + ldc.l er0, vbr + set_grs_a5a5 + mov.l #.Ltgt_7:32, @vector_area+0x300 + set_ccr_zero + + jmp @@0x300 + fail +.Ltgt_7: + test_cc_clear + test_grs_a5a5 + stc.l vbr, er0 + test_h_gr32 vector_area, er0 + +.endif ; h8sx jmp_24: set_grs_a5a5 ; Fill all general regs with a fixed pattern @@ -52,7 +72,7 @@ jmp_24: test_gr_a5a5 6 test_gr_a5a5 7 -.if (sim_cpu) ; Non-zero means h8300h, h8300s, or h8sx +.if (sim_cpu) ; Non-zero means h8300h, h8300s, or h8sx jmp_reg: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero @@ -72,7 +92,7 @@ jmp_reg: test_h_gr32 .Ltgt_reg er5 test_gr_a5a5 6 test_gr_a5a5 7 -.endif +.endif ; not h8300 .if (sim_cpu == h8sx) jmp_32: @@ -95,7 +115,7 @@ jmp_32: test_gr_a5a5 5 test_gr_a5a5 6 test_gr_a5a5 7 -.endif +.endif ; h8sx pass exit 0 diff --git a/sim/testsuite/sim/h8300/ldm.s b/sim/testsuite/sim/h8300/ldm.s index c26349fe618..c8162217064 100644 --- a/sim/testsuite/sim/h8300/ldm.s +++ b/sim/testsuite/sim/h8300/ldm.s @@ -180,8 +180,9 @@ ldm_4reg: test_h_gr32 _stack+20, er7 .endif -.if (sim_cpu == h8300) +pushpop: set_grs_a5a5 +.if (sim_cpu == h8300) mov #_stack_top, r7 mov #12, r1 mov #34, r2 @@ -204,8 +205,6 @@ ldm_4reg: cmp.w r0, r7 bne fail1 .else -pushpop: - set_grs_a5a5 mov #_stack_top, er7 mov #12, er1 mov #34, er2 diff --git a/sim/testsuite/sim/h8300/mac.s b/sim/testsuite/sim/h8300/mac.s index 0388b98a810..d60fe30da29 100644 --- a/sim/testsuite/sim/h8300/mac.s +++ b/sim/testsuite/sim/h8300/mac.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'mac' -# mach(): h8300h h8300s h8sx +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/mul.s b/sim/testsuite/sim/h8300/mul.s new file mode 100644 index 00000000000..70ab7ec1208 --- /dev/null +++ b/sim/testsuite/sim/h8300/mul.s @@ -0,0 +1,474 @@ +# Hitachi H8 testcase 'muls', 'muls/u', mulu', 'mulu/u', 'mulxs', 'mulxu' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) +muls_w_reg_reg: + set_grs_a5a5 + + ;; muls.w rs, rd + mov.w #32, r1 + mov.w #-2, r2 + set_ccr_zero + muls.w r2, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 -64 r1 + test_h_gr32 0xa5a5fffe er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +muls_w_imm4_reg: + set_grs_a5a5 + + ;; muls.w xx:4, rd + mov.w #32, r1 + set_ccr_zero + muls.w #-2:4, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 -64 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +muls_l_reg_reg: + set_grs_a5a5 + + ;; muls.l ers, erd + mov.l #320000, er1 + mov.l #-2, er2 + set_ccr_zero + muls.l er2, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 -640000 er1 + test_h_gr32 -2 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +muls_l_imm4_reg: + set_grs_a5a5 + + ;; muls.l xx:4, rd + mov.l #320000, er1 + set_ccr_zero + muls.l #-2:4, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 -640000 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +muls_u_l_reg_reg: + set_grs_a5a5 + + ;; muls/u.l ers, erd + mov.l #0x10000000, er1 + mov.l #-16, er2 + set_ccr_zero + muls/u.l er2, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 -1 er1 + test_h_gr32 -16 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +muls_u_l_imm4_reg: + set_grs_a5a5 + + ;; muls/u.l xx:4, rd + mov.l #0xffffffff, er1 + set_ccr_zero + muls/u.l #2:4, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 -1 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mulu_w_reg_reg: + set_grs_a5a5 + + ;; mulu.w rs, rd + mov.w #32, r1 + mov.w #-2, r2 + set_ccr_zero + mulu.w r2, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 -64 r1 + test_h_gr32 0xa5a5fffe er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mulu_w_imm4_reg: + set_grs_a5a5 + + ;; mulu.w xx:4, rd + mov.w #32, r1 + set_ccr_zero + mulu.w #-2:4, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 0x1c0 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mulu_l_reg_reg: + set_grs_a5a5 + + ;; mulu.l ers, erd + mov.l #320000, er1 + mov.l #-2, er2 + set_ccr_zero + mulu.l er2, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 -640000 er1 + test_h_gr32 -2 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mulu_l_imm4_reg: + set_grs_a5a5 + + ;; mulu.l xx:4, rd + mov.l #320000, er1 + set_ccr_zero + mulu.l #-2:4, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 0x445c00 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mulu_u_l_reg_reg: + set_grs_a5a5 + + ;; mulu/u.l ers, erd + mov.l #0x10000000, er1 + mov.l #16, er2 + set_ccr_zero + mulu/u.l er2, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 1 er1 + test_h_gr32 16 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mulu_u_l_imm4_reg: + set_grs_a5a5 + + ;; mulu/u.l xx:4, rd + mov.l #0xffffffff, er1 + set_ccr_zero + mulu/u.l #2:4, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 0x1 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu) ; not equal to zero ie. not h8 +mulxs_b_reg_reg: + set_grs_a5a5 + + ;; mulxs.b rs, rd + mov.b #32, r1l + mov.b #-2, r2l + set_ccr_zero + mulxs.b r2l, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 -64 r1 + test_h_gr32 0xa5a5a5fe er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mulxs_b_imm4_reg: + set_grs_a5a5 + + ;; mulxs.b xx:4, rd + mov.w #32, r1 + set_ccr_zero + mulxs.b #-2:4, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 -64 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + +mulxs_w_reg_reg: + set_grs_a5a5 + + ;; mulxs.w ers, erd + mov.w #0x1000, r1 + mov.w #-0x1000, r2 + set_ccr_zero + mulxs.w r2, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 0xff000000 er1 + test_h_gr32 0xa5a5f000 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mulxs_w_imm4_reg: + set_grs_a5a5 + + ;; mulxs.w xx:4, rd + mov.w #-1, r1 + set_ccr_zero + mulxs.w #2:4, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 -2 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx +.endif ; not h8 + +mulxu_b_reg_reg: + set_grs_a5a5 + + ;; mulxu.b rs, rd + mov.b #32, r1l + mov.b #-2, r2l + set_ccr_zero + mulxu.b r2l, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 0x1fc0 r1 + test_h_gr16 0xa5fe r2 +.if (sim_cpu) + test_h_gr32 0xa5a5a5fe er2 +.endif + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu) ; not h8 +.if (sim_cpu == h8sx) +mulxu_b_imm4_reg: + set_grs_a5a5 + + ;; mulxu.b xx:4, rd + mov.b #32, r1l + set_ccr_zero + mulxu.b #-2:4, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 0x1c0 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + +mulxu_w_reg_reg: + set_grs_a5a5 + + ;; mulxu.w ers, erd + mov.w #0x1000, r1 + mov.w #-0x1000, r2 + set_ccr_zero + mulxu.w r2, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 0x0f000000 er1 + test_h_gr32 0xa5a5f000 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mulxu_w_imm4_reg: + set_grs_a5a5 + + ;; mulxu.w xx:4, rd + mov.w #-1, r1 + set_ccr_zero + mulxu.w #2:4, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 0x1fffe er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx +.endif ; not h8 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/orb.s b/sim/testsuite/sim/h8300/orb.s index fd06f08fb98..72da8e63a37 100644 --- a/sim/testsuite/sim/h8300/orb.s +++ b/sim/testsuite/sim/h8300/orb.s @@ -24,6 +24,9 @@ # or.b reg8, @+erd ; 0 1 7 9 9 rd 4 rs # or.b reg8, @-erd ; 0 1 7 9 b rd 4 rs # + # orc #xx:8, ccr + # orc #xx:8, exr + # Coming soon: # ... @@ -455,6 +458,8 @@ or_b_reg8_rdpredec: fail .L10: +.endif + orc_imm8_ccr: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero @@ -486,8 +491,42 @@ orc_imm8_ccr: test_gr_a5a5 6 test_gr_a5a5 7 -.endif +.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr +orc_imm8_exr: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ldc #0, exr + stc exr, r0l + test_h_gr8 0, r0l + + ;; orc #xx:8,exr + + orc #0x1, exr + stc exr,r0l + test_h_gr8 1, r0l + + orc #0x2, exr + stc exr,r0l + test_h_gr8 3, r0l + + orc #0x4, exr + stc exr,r0l + test_h_gr8 7, r0l + orc #0x80, exr + stc exr,r0l + test_h_gr8 0x87, r0l + + test_h_gr32 0xa5a5a587 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; not h8300 or h8300h + pass exit 0 diff --git a/sim/testsuite/sim/h8300/stack.s b/sim/testsuite/sim/h8300/stack.s new file mode 100644 index 00000000000..dd53445003e --- /dev/null +++ b/sim/testsuite/sim/h8300/stack.s @@ -0,0 +1,445 @@ +# Hitachi H8 testcase 'ldc' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.data + .align 4 +stack: +.if (sim_cpu == h8300) + .fill 128, 2, 0 +.else + .fill 128, 4, 0 +.endif +stacktop: + + .text + +push_w: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero +.if (sim_cpu == h8300) + mov.w #stacktop, r7 +.else + mov.l #stacktop, er7 +.endif + push.w r0 ; a5a5 is negative + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + push.w r1 + push.w r2 + push.w r3 + + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + + mov @stacktop-2, r0 + test_gr_a5a5 0 + mov @stacktop-4, r0 + test_gr_a5a5 0 + mov @stacktop-6, r0 + test_gr_a5a5 0 + mov @stacktop-8, r0 + test_gr_a5a5 0 + + mov.w #1, r1 + mov.w #2, r2 + mov.w #3, r3 + mov.w #4, r4 + + push.w r1 ; #1 is non-negative, non-zero + test_cc_clear + + push.w r2 + push.w r3 + push.w r4 + + test_h_gr16 1 r1 + test_h_gr16 2 r2 + test_h_gr16 3 r3 + test_h_gr16 4 r4 + + mov @stacktop-10, r0 + test_h_gr16 1 r0 + mov @stacktop-12, r0 + test_h_gr16 2 r0 + mov @stacktop-14, r0 + test_h_gr16 3 r0 + mov @stacktop-16, r0 + test_h_gr16 4 r0 + +.if (sim_cpu == h8300) + test_h_gr16 4 r0 + test_h_gr16 1 r1 + test_h_gr16 2 r2 + test_h_gr16 3 r3 + test_h_gr16 4 r4 +;;; test_h_gr16 stacktop-16 r7 ; FIXME +.else + test_h_gr32 0xa5a50004 er0 + test_h_gr32 0xa5a50001 er1 + test_h_gr32 0xa5a50002 er2 + test_h_gr32 0xa5a50003 er3 + test_h_gr32 0xa5a50004 er4 + test_h_gr32 stacktop-16 er7 +.endif + test_gr_a5a5 5 + test_gr_a5a5 6 + +pop_w: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero +.if (sim_cpu == h8300) + mov.w #stacktop-16, r7 +.else + mov.l #stacktop-16, er7 +.endif + pop.w r4 + pop.w r3 + pop.w r2 + pop.w r1 ; Should set all flags zero + test_cc_clear + + test_h_gr16 1 r1 + test_h_gr16 2 r2 + test_h_gr16 3 r3 + test_h_gr16 4 r4 + + pop.w r4 + pop.w r3 + pop.w r2 + pop.w r1 ; a5a5 is negative + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 +.if (sim_cpu == h8300) +;;; test_h_gr16 stacktop r7 ; FIXME +.else + test_h_gr32 stacktop er7 +.endif + +.if (sim_cpu) ; non-zero means not h8300 +push_l: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + mov.l #stacktop, er7 + push.l er0 ; a5a5 is negative + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + push.l er1 + push.l er2 + push.l er3 + + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + + mov @stacktop-4, er0 + test_gr_a5a5 0 + mov @stacktop-8, er0 + test_gr_a5a5 0 + mov @stacktop-12, er0 + test_gr_a5a5 0 + mov @stacktop-16, er0 + test_gr_a5a5 0 + + mov #1, er1 + mov #2, er2 + mov #3, er3 + mov #4, er4 + + push.l er1 ; #1 is non-negative, non-zero + test_cc_clear + + push.l er2 + push.l er3 + push.l er4 + + test_h_gr32 1 er1 + test_h_gr32 2 er2 + test_h_gr32 3 er3 + test_h_gr32 4 er4 + + mov @stacktop-20, er0 + test_h_gr32 1 er0 + mov @stacktop-24, er0 + test_h_gr32 2 er0 + mov @stacktop-28, er0 + test_h_gr32 3 er0 + mov @stacktop-32, er0 + test_h_gr32 4 er0 + + test_h_gr32 4 er0 + test_h_gr32 1 er1 + test_h_gr32 2 er2 + test_h_gr32 3 er3 + test_h_gr32 4 er4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_h_gr32 stacktop-32 er7 + +pop_l: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + mov.l #stacktop-32, er7 + pop.l er4 + pop.l er3 + pop.l er2 + pop.l er1 ; Should set all flags zero + test_cc_clear + + test_h_gr32 1 er1 + test_h_gr32 2 er2 + test_h_gr32 3 er3 + test_h_gr32 4 er4 + + pop.l er4 + pop.l er3 + pop.l er2 + pop.l er1 ; a5a5 is negative + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_h_gr32 stacktop er7 +.endif + + ;; Jump over subroutine + jmp _bsr + +bsr_jsr_func: + test_ccr 0 ; call should not affect ccr + mov.w #0, r0 + mov.w #1, r1 + mov.w #2, r2 + mov.w #3, r3 + mov.w #4, r4 + mov.w #5, r5 + mov.w #6, r6 + rts + +_bsr: set_grs_a5a5 +.if (sim_cpu == h8300) + mov.w #stacktop, r7 +.else + mov.l #stacktop, er7 +.endif + set_ccr_zero + bsr bsr_jsr_func + + test_h_gr16 0 r0 + test_h_gr16 1 r1 + test_h_gr16 2 r2 + test_h_gr16 3 r3 + test_h_gr16 4 r4 + test_h_gr16 5 r5 + test_h_gr16 6 r6 +.if (sim_cpu == h8300) +;;; test_h_gr16 stacktop, r7 ; FIXME +.else + test_h_gr32 stacktop, er7 +.endif + +_jsr: set_grs_a5a5 +.if (sim_cpu == h8300) + mov.w #stacktop, r7 +.else + mov.l #stacktop, er7 +.endif + set_ccr_zero + jsr bsr_jsr_func + + test_h_gr16 0 r0 + test_h_gr16 1 r1 + test_h_gr16 2 r2 + test_h_gr16 3 r3 + test_h_gr16 4 r4 + test_h_gr16 5 r5 + test_h_gr16 6 r6 +.if (sim_cpu == h8300) +;;; test_h_gr16 stacktop, r7 ; FIXME +.else + test_h_gr32 stacktop, er7 +.endif + +.if (sim_cpu) ; not zero ie. not h8300 +_trapa: + set_grs_a5a5 + mov.l #trap_handler, er7 ; trap vector + mov.l er7, @0x2c + mov.l #stacktop, er7 + set_ccr_zero + trapa #3 + + test_cc_clear ; ccr should be restored by rte + test_h_gr16 0x10 r0 + test_h_gr16 0x11 r1 + test_h_gr16 0x12 r2 + test_h_gr16 0x13 r3 + test_h_gr16 0x14 r4 + test_h_gr16 0x15 r5 + test_h_gr16 0x16 r6 + test_h_gr32 stacktop er7 +.endif + +.if (sim_cpu == h8sx) +_rtsl: ; Test rts/l insn. + set_grs_a5a5 + mov #0,r0l + mov #1,r1l + mov #2,r2l + mov #3,r3l + mov #4,r4l + mov #5,r5l + mov #6,r6l + mov #stacktop, er7 + + jsr rtsl1_func + test_h_gr32 0xa5a5a500 er0 + test_h_gr32 0xa5a5a501 er1 + test_h_gr32 0xa5a5a502 er2 + test_h_gr32 0xa5a5a503 er3 + test_h_gr32 0xa5a5a504 er4 + test_h_gr32 0xa5a5a505 er5 + test_h_gr32 0xa5a5a506 er6 + test_h_gr32 stacktop er7 + + jsr rtsl2_func + test_h_gr32 0xa5a5a500 er0 + test_h_gr32 0xa5a5a501 er1 + test_h_gr32 0xa5a5a502 er2 + test_h_gr32 0xa5a5a503 er3 + test_h_gr32 0xa5a5a504 er4 + test_h_gr32 0xa5a5a505 er5 + test_h_gr32 0xa5a5a506 er6 + test_h_gr32 stacktop er7 + + jsr rtsl3_func + test_h_gr32 0xa5a5a500 er0 + test_h_gr32 0xa5a5a501 er1 + test_h_gr32 0xa5a5a502 er2 + test_h_gr32 0xa5a5a503 er3 + test_h_gr32 0xa5a5a504 er4 + test_h_gr32 0xa5a5a505 er5 + test_h_gr32 0xa5a5a506 er6 + test_h_gr32 stacktop er7 + + jsr rtsl4_func + test_h_gr32 0xa5a5a500 er0 + test_h_gr32 0xa5a5a501 er1 + test_h_gr32 0xa5a5a502 er2 + test_h_gr32 0xa5a5a503 er3 + test_h_gr32 0xa5a5a504 er4 + test_h_gr32 0xa5a5a505 er5 + test_h_gr32 0xa5a5a506 er6 + test_h_gr32 stacktop er7 +.endif ; h8sx + + pass + + exit 0 + + ;; Handler for a software exception (trap). +trap_handler: + ;; Test the 'i' interrupt mask flag. + stc ccr, r0l + test_h_gr8 0x80, r0l + ;; Change the registers (so we know we've been here) + mov.w #0x10, r0 + mov.w #0x11, r1 + mov.w #0x12, r2 + mov.w #0x13, r3 + mov.w #0x14, r4 + mov.w #0x15, r5 + mov.w #0x16, r6 + ;; Change the ccr (which will be restored by RTE) + orc #0xff, ccr + rte + +.if (sim_cpu == h8sx) + ;; Functions for testing rts/l +rtsl1_func: ; Save and restore R0 + push.l er0 + ;; Now modify it, and verify the modification. + mov #0xfeedface, er0 + test_h_gr32 0xfeedface, er0 + ;; Then use rts/l to restore them and return. + rts/l er0 + +rtsl2_func: ; Save and restore R5 and R6 + push.l er5 + push.l er6 + ;; Now modify them, and verify the modification. + mov #0xdeadbeef, er5 + mov #0xfeedface, er6 + test_h_gr32 0xdeadbeef, er5 + test_h_gr32 0xfeedface, er6 + ;; Then use rts/l to restore them and return. + rts/l (er5-er6) + +rtsl3_func: ; Save and restore R4, R5, and R6 + push.l er4 + push.l er5 + push.l er6 + ;; Now modify them, and verify the modification. + mov #0xdeafcafe, er4 + mov #0xdeadbeef, er5 + mov #0xfeedface, er6 + test_h_gr32 0xdeafcafe, er4 + test_h_gr32 0xdeadbeef, er5 + test_h_gr32 0xfeedface, er6 + ;; Then use rts/l to restore them and return. + rts/l (er4-er6) + +rtsl4_func: ; Save and restore R0 - R3 + push.l er0 + push.l er1 + push.l er2 + push.l er3 + ;; Now modify them, and verify the modification. + mov #0xdadacafe, er0 + mov #0xfeedbeef, er1 + mov #0xdeadface, er2 + mov #0xf00dd00d, er3 + test_h_gr32 0xdadacafe, er0 + test_h_gr32 0xfeedbeef, er1 + test_h_gr32 0xdeadface, er2 + test_h_gr32 0xf00dd00d, er3 + ;; Then use rts/l to restore them and return. + rts/l (er0-er3) +.endif ; h8sx diff --git a/sim/testsuite/sim/h8300/subs.s b/sim/testsuite/sim/h8300/subs.s new file mode 100644 index 00000000000..1bb5eea754d --- /dev/null +++ b/sim/testsuite/sim/h8300/subs.s @@ -0,0 +1,74 @@ +# Hitachi H8 testcase 'subs' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # subs #1, erd ; 1 b 0 0erd + # subs #2, erd ; 1 b 8 0erd + # subs #4, erd ; 1 b 9 0erd + # + + start +.if (sim_cpu) ; 32 bit only +subs_1: + set_grs_a5a5 + set_ccr_zero + + subs #1, er0 + + test_cc_clear ; subs should not affect any condition codes + test_h_gr32 0xa5a5a5a4 er0 ; result of subs #1 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subs_2: + set_grs_a5a5 + set_ccr_zero + + subs #2, er0 + + test_cc_clear ; subs should not affect any condition codes + test_h_gr32 0xa5a5a5a3 er0 ; result of subs #2 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subs_4: + set_grs_a5a5 + set_ccr_zero + + subs #4, er0 + + test_cc_clear ; subs should not affect any condition codes + test_h_gr32 0xa5a5a5a1 er0 ; result of subs #4 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass +.endif + exit 0 diff --git a/sim/testsuite/sim/h8300/subx.s b/sim/testsuite/sim/h8300/subx.s new file mode 100644 index 00000000000..78656bc2fd8 --- /dev/null +++ b/sim/testsuite/sim/h8300/subx.s @@ -0,0 +1,1010 @@ +# Hitachi H8 testcase 'subx' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # subx.b #xx:8, rd8 ; b rd8 xxxxxxxx + # subx.b #xx:8, @erd ; 7 d erd ???? b ???? xxxxxxxx + # subx.b #xx:8, @erd- ; 0 1 7 6 6 c erd 1??? b ???? xxxxxxxx + # subx.b rs8, rd8 ; 1 e rs8 rd8 + # subx.b rs8, @erd ; 7 d erd ???? 1 e rs8 ???? + # subx.b rs8, @erd- ; 0 1 7 6 6 c erd 1??? 1 e rs8 ???? + # subx.b @ers, rd8 ; 7 c ers ???? 1 e ???? rd8 + # subx.b @ers-, rd8 ; 0 1 7 6 6 c ers 00?? 1 e ???? rd8 + # subx.b @ers, @erd ; 0 1 7 4 6 8 ers d 0 erd 3 ???? + # subx.b @ers-, @erd- ; 0 1 7 6 6 c ers d a erd 3 ???? + # + # word ops + # long ops + +.data +byte_src: .byte 0x5 +byte_dest: .byte 0 + + .align 2 +word_src: .word 0x505 +word_dest: .word 0 + + .align 4 +long_src: .long 0x50505 +long_dest: .long 0 + + + start + +subx_b_imm8_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; subx.b #xx:8,Rd ; Subx with carry initially zero. + subx.b #5, r0l ; Immediate 8-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0xa5a0 r0 ; sub result: a5 - 5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5a0 er0 ; sub result: a5 - 5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_b_imm8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; subx.b #xx:8,Rd ; Subx with carry initially one. + set_carry_flag + subx.b #4, r0l ; Immediate 8-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0xa5a0 r0 ; sub result: a5 - (4 + 1) +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5a0 er0 ; sub result: a5 - (4 + 1) +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +subx_b_imm8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b #xx:8,@eRd ; Subx to register indirect + mov #byte_dest, er0 + mov.b #0xa5, @er0 + set_ccr_zero + subx.b #5, @er0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 still contains subress + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.b #0xa0, @byte_dest + beq .Lb1 + fail +.Lb1: + +subx_b_imm8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b #xx:8,@eRd- ; Subx to register post-decrement + mov #byte_dest, er0 + mov.b #0xa5, @er0 + set_ccr_zero + subx.b #5, @er0- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest-1 er0 ; er0 contains subress minus one + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.b #0xa0, @byte_dest + beq .Lb2 + fail +.Lb2: +.endif + +subx_b_reg8_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b Rs,Rd ; subx with carry initially zero + mov.b #5, r0h + set_ccr_zero + subx.b r0h, r0l ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0x05a0 r0 ; sub result: a5 - 5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a505a0 er0 ; sub result: a5 - 5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_b_reg8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b Rs,Rd ; subx with carry initially one + mov.b #4, r0h + set_ccr_zero + set_carry_flag + subx.b r0h, r0l ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0x04a0 r0 ; sub result: a5 - (4 + 1) +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a504a0 er0 ; sub result: a5 - (4 + 1) +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +subx_b_reg8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b rs8,@eRd ; Subx to register indirect + mov #byte_dest, er0 + mov.b #0xa5, @er0 + mov.b #5, r1l + set_ccr_zero + subx.b r1l, @er0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 still contains subress + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.b #0xa0, @byte_dest + beq .Lb3 + fail +.Lb3: + +subx_b_reg8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b rs8,@eRd- ; Subx to register post-decrement + mov #byte_dest, er0 + mov.b #0xa5, @er0 + mov.b #5, r1l + set_ccr_zero + subx.b r1l, @er0- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest-1 er0 ; er0 contains subress minus one + test_h_gr32 0xa5a5a505 er1 ; er1 contains the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.b #0xa0, @byte_dest + beq .Lb4 + fail +.Lb4: + +subx_b_rsind_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b @eRs,rd8 ; Subx from reg indirect to reg + mov #byte_src, er0 + set_ccr_zero + subx.b @er0, r1l + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_src er0 ; er0 still contains subress + test_h_gr32 0xa5a5a5a0 er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_b_rspostdec_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b @eRs-,rd8 ; Subx to register post-decrement + mov #byte_src, er0 + set_ccr_zero + subx.b @er0-, r1l + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_src-1 er0 ; er0 contains subress minus one + test_h_gr32 0xa5a5a5a0 er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_b_rsind_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b @eRs,rd8 ; Subx from reg indirect to reg + mov #byte_src, er0 + mov #byte_dest, er1 + mov.b #0xa5, @er1 + set_ccr_zero + subx.b @er0, @er1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_src er0 ; er0 still contains src subress + test_h_gr32 byte_dest er1 ; er1 still contains dst subress + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the sub to memory. + cmp.b #0xa0, @byte_dest + beq .Lb5 + fail +.Lb5: + +subx_b_rspostdec_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + mov #byte_src, er0 + mov #byte_dest, er1 + mov.b #0xa5, @er1 + set_ccr_zero + ;; subx.b @eRs-,@erd- ; Subx post-decrement to post-decrement + subx.b @er0-, @er1- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_src-1 er0 ; er0 contains src subress minus one + test_h_gr32 byte_dest-1 er1 ; er1 contains dst subress minus one + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the sub to memory. + cmp.b #0xa0, @byte_dest + beq .Lb6 + fail +.Lb6: + +subx_w_imm16_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; subx.w #xx:16,Rd ; Subx with carry initially zero. + subx.w #0x505, r0 ; Immediate 16-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0xa0a0 r0 ; sub result: 0xa5a5 + 0x505 + test_h_gr32 0xa5a5a0a0 er0 ; sub result: 0xa5a5 + 0x505 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_w_imm16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; subx.w #xx:16,Rd ; Subx with carry initially one. + set_carry_flag + subx.w #0x504, r0 ; Immediate 16-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0xa0a0 r0 ; sub result: 0xa5a5 + 0x505 + 1 + test_h_gr32 0xa5a5a0a0 er0 ; sub result: 0xa5a5 + 0x505 + 1 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_w_imm16_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w #xx:16,@eRd ; Subx to register indirect + mov #word_dest, er0 + mov.w #0xa5a5, @er0 + set_ccr_zero + subx.w #0x505, @er0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_dest er0 ; er0 still contains subress + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.w #0xa0a0, @word_dest + beq .Lw1 + fail +.Lw1: + +subx_w_imm16_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w #xx:16,@eRd- ; Subx to register post-decrement + mov #word_dest, er0 + mov.w #0xa5a5, @er0 + set_ccr_zero + subx.w #0x505, @er0- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_dest-2 er0 ; er0 contains subress minus one + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.w #0xa0a0, @word_dest + beq .Lw2 + fail +.Lw2: + +subx_w_reg16_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w Rs,Rd ; subx with carry initially zero + mov.w #0x505, e0 + set_ccr_zero + subx.w e0, r0 ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0x0505a0a0 er0 ; sub result: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_w_reg16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w Rs,Rd ; subx with carry initially one + mov.w #0x504, e0 + set_ccr_zero + set_carry_flag + subx.w e0, r0 ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0x0504a0a0 er0 ; sub result: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_w_reg16_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w rs8,@eRd ; Subx to register indirect + mov #word_dest, er0 + mov.w #0xa5a5, @er0 + mov.w #0x505, r1 + set_ccr_zero + subx.w r1, @er0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_dest er0 ; er0 still contains subress + test_h_gr32 0xa5a50505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.w #0xa0a0, @word_dest + beq .Lw3 + fail +.Lw3: + +subx_w_reg16_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w rs8,@eRd- ; Subx to register post-decrement + mov #word_dest, er0 + mov.w #0xa5a5, @er0 + mov.w #0x505, r1 + set_ccr_zero + subx.w r1, @er0- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_dest-2 er0 ; er0 contains subress minus one + test_h_gr32 0xa5a50505 er1 ; er1 contains the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.w #0xa0a0, @word_dest + beq .Lw4 + fail +.Lw4: + +subx_w_rsind_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w @eRs,rd8 ; Subx from reg indirect to reg + mov #word_src, er0 + set_ccr_zero + subx.w @er0, r1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_src er0 ; er0 still contains subress + test_h_gr32 0xa5a5a0a0 er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_w_rspostdec_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w @eRs-,rd8 ; Subx to register post-decrement + mov #word_src, er0 + set_ccr_zero + subx.w @er0-, r1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_src-2 er0 ; er0 contains subress minus one + test_h_gr32 0xa5a5a0a0 er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_w_rsind_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w @eRs,rd8 ; Subx from reg indirect to reg + mov #word_src, er0 + mov #word_dest, er1 + mov.w #0xa5a5, @er1 + set_ccr_zero + subx.w @er0, @er1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_src er0 ; er0 still contains src subress + test_h_gr32 word_dest er1 ; er1 still contains dst subress + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the sub to memory. + cmp.w #0xa0a0, @word_dest + beq .Lw5 + fail +.Lw5: + +subx_w_rspostdec_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w @eRs-,rd8 ; Subx to register post-decrement + mov #word_src, er0 + mov #word_dest, er1 + mov.w #0xa5a5, @er1 + set_ccr_zero + subx.w @er0-, @er1- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_src-2 er0 ; er0 contains src subress minus one + test_h_gr32 word_dest-2 er1 ; er1 contains dst subress minus one + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the sub to memory. + cmp.w #0xa0a0, @word_dest + beq .Lw6 + fail +.Lw6: + +subx_l_imm32_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; subx.l #xx:32,Rd ; Subx with carry initially zero. + subx.l #0x50505, er0 ; Immediate 32-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0xa5a0a0a0 er0 ; sub result: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_l_imm32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; subx.l #xx:32,Rd ; Subx with carry initially one. + set_carry_flag + subx.l #0x50504, er0 ; Immediate 32-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0xa5a0a0a0 er0 ; sub result: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_l_imm32_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l #xx:32,@eRd ; Subx to register indirect + mov #long_dest, er0 + mov.l #0xa5a5a5a5, @er0 + set_ccr_zero + subx.l #0x50505, @er0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_dest er0 ; er0 still contains subress + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.l #0xa5a0a0a0, @long_dest + beq .Ll1 + fail +.Ll1: + +subx_l_imm32_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l #xx:32,@eRd- ; Subx to register post-decrement + mov #long_dest, er0 + mov.l #0xa5a5a5a5, @er0 + set_ccr_zero + subx.l #0x50505, @er0- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_dest-4 er0 ; er0 contains subress minus one + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.l #0xa5a0a0a0, @long_dest + beq .Ll2 + fail +.Ll2: + +subx_l_reg32_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l Rs,Rd ; subx with carry initially zero + mov.l #0x50505, er0 + set_ccr_zero + subx.l er0, er1 ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0x50505 er0 ; sub load + test_h_gr32 0xa5a0a0a0 er1 ; sub result: + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_l_reg32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l Rs,Rd ; subx with carry initially one + mov.l #0x50504, er0 + set_ccr_zero + set_carry_flag + subx.l er0, er1 ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0x50504 er0 ; sub result: + test_h_gr32 0xa5a0a0a0 er1 ; sub result: + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_l_reg32_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l rs8,@eRd ; Subx to register indirect + mov #long_dest, er0 + mov.l er1, @er0 + mov.l #0x50505, er1 + set_ccr_zero + subx.l er1, @er0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_dest er0 ; er0 still contains subress + test_h_gr32 0x50505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.l #0xa5a0a0a0, @long_dest + beq .Ll3 + fail +.Ll3: + +subx_l_reg32_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l rs8,@eRd- ; Subx to register post-decrement + mov #long_dest, er0 + mov.l er1, @er0 + mov.l #0x50505, er1 + set_ccr_zero + subx.l er1, @er0- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_dest-4 er0 ; er0 contains subress minus one + test_h_gr32 0x50505 er1 ; er1 contains the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.l #0xa5a0a0a0, @long_dest + beq .Ll4 + fail +.Ll4: + +subx_l_rsind_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l @eRs,rd8 ; Subx from reg indirect to reg + mov #long_src, er0 + set_ccr_zero + subx.l @er0, er1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_src er0 ; er0 still contains subress + test_h_gr32 0xa5a0a0a0 er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_l_rspostdec_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l @eRs-,rd8 ; Subx to register post-decrement + mov #long_src, er0 + set_ccr_zero + subx.l @er0-, er1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_src-4 er0 ; er0 contains subress minus one + test_h_gr32 0xa5a0a0a0 er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_l_rsind_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l @eRs,rd8 ; Subx from reg indirect to reg + mov #long_src, er0 + mov #long_dest, er1 + mov.l er2, @er1 + set_ccr_zero + subx.l @er0, @er1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_src er0 ; er0 still contains src subress + test_h_gr32 long_dest er1 ; er1 still contains dst subress + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the sub to memory. + cmp.l #0xa5a0a0a0, @long_dest + beq .Ll5 + fail +.Ll5: + +subx_l_rspostdec_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l @eRs-,rd8 ; Subx to register post-decrement + mov #long_src, er0 + mov #long_dest, er1 + mov.l er2, @er1 + set_ccr_zero + subx.l @er0-, @er1- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_src-4 er0 ; er0 contains src subress minus one + test_h_gr32 long_dest-4 er1 ; er1 contains dst subress minus one + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the sub to memory. + cmp.l #0xa5a0a0a0, @long_dest + beq .Ll6 + fail +.Ll6: +.endif + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/tas.s b/sim/testsuite/sim/h8300/tas.s new file mode 100644 index 00000000000..b8aebd80dee --- /dev/null +++ b/sim/testsuite/sim/h8300/tas.s @@ -0,0 +1,80 @@ +# Hitachi H8 testcase 'tas' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +byte_dst: .byte 0 + + start + +tas_ind: ; test and set instruction + set_grs_a5a5 + mov #byte_dst, er4 + set_ccr_zero + ;; tas @erd + tas @er4 ; should set zero flag + test_carry_clear + test_neg_clear + test_ovf_clear + test_zero_set + + tas @er4 ; should clear zero, set neg + test_carry_clear + test_neg_set + test_ovf_clear + test_zero_clear + + test_gr_a5a5 0 ; general regs have not been modified + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_h_gr32 byte_dst, er4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + mov.b @byte_dst, r0l ; test variable has MSB set? + test_h_gr8 0x80 r0l + +.if (sim_cpu == h8sx) ; h8sx can use any register for tas +tas_h8sx: ; test and set instruction + mov.b #0, @byte_dst + set_grs_a5a5 + mov #byte_dst, er3 + set_ccr_zero + ;; tas @erd + tas @er3 ; should set zero flag + test_carry_clear + test_neg_clear + test_ovf_clear + test_zero_set + + tas @er3 ; should clear zero, set neg + test_carry_clear + test_neg_set + test_ovf_clear + test_zero_clear + + test_gr_a5a5 0 ; general regs have not been modified + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 byte_dst, er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + mov.b @byte_dst, r0l ; test variable has MSB set? + test_h_gr8 0x80 r0l +.endif ; h8sx + + pass + exit 0 diff --git a/sim/testsuite/sim/h8300/testutils.inc b/sim/testsuite/sim/h8300/testutils.inc index fb8bdcae1be..9c2c27a8d78 100644 --- a/sim/testsuite/sim/h8300/testutils.inc +++ b/sim/testsuite/sim/h8300/testutils.inc @@ -226,24 +226,34 @@ _main: ldc #0, ccr .endm -; Set carry flag to value - .macro set_carry_flag val - .data -scf\@: .byte 0 - .text - mov.b r0l, @scf\@ - mov.b #\val:8, r0l - or.b r0l, r0l - beq .Lccf\@ ; clear - stc ccr, r0l ; set - or.b #0x1, r0l - jmp .Lecf\@ -.Lccf\@: ; clear - stc ccr, r0l - and.b #0xfe, r0l -.Lecf\@: - ldc r0l, ccr - mov @scf\@, r0l +; Set carry flag true + .macro set_carry_flag + orc #1, ccr + .endm + +; Clear carry flag + .macro clear_carry_flag + andc 0xfe, ccr + .endm + +; Set zero flag true + .macro set_zero_flag + orc #4, ccr + .endm + +; Clear zero flag + .macro clear_zero_flag + andc 0xfb, ccr + .endm + +; Set neg flag true + .macro set_neg_flag + orc #8, ccr + .endm + +; Clear neg flag + .macro clear_neg_flag + andc 0xf7, ccr .endm ; Test that carry flag is clear diff --git a/sim/testsuite/sim/h8300/xorb.s b/sim/testsuite/sim/h8300/xorb.s index 7005a95c609..337c3968a47 100644 --- a/sim/testsuite/sim/h8300/xorb.s +++ b/sim/testsuite/sim/h8300/xorb.s @@ -24,6 +24,8 @@ # xor.b reg8, @+erd ; 0 1 7 9 9 rd 5 rs # xor.b reg8, @-erd ; 0 1 7 9 b rd 5 rs # + # xorc #xx:8, ccr ; + # xorc #xx:8, exr ; # Coming soon: # ... @@ -281,6 +283,8 @@ xor_b_reg8_rdpostdec: fail .L6: +.endif ; h8sx + xorc_imm8_ccr: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero @@ -320,8 +324,55 @@ xorc_imm8_ccr: test_gr_a5a5 6 test_gr_a5a5 7 -.endif +.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr +xorc_imm8_exr: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ldc #0, exr + stc exr, r0l + test_h_gr8 0, r0l + set_ccr_zero + ;; xorc #xx:8,exr + + xorc #0x80, exr + test_cc_clear + stc exr, r0l + test_h_gr8 0x80, r0l + xorc #0x80, exr + stc exr, r0l + test_h_gr8 0, r0l + + xorc #0x4, exr + stc exr, r0l + test_h_gr8 4, r0l + xorc #0x4, exr + stc exr, r0l + test_h_gr8 0, r0l + + xorc #0x2, exr ; Immediate 8-bit operand (overflow flag) + stc exr, r0l + test_h_gr8 2, r0l + xorc #0x2, exr + stc exr, r0l + test_h_gr8 0, r0l + + xorc #0x1, exr ; Immediate 8-bit operand (carry flag) + stc exr, r0l + test_h_gr8 1, r0l + xorc #0x1, exr + stc exr, r0l + test_h_gr8 0, r0l + + test_h_gr32 0xa5a5a500 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; not h8300 or h8300h + pass exit 0 -- 2.30.2