From 3e167f73d3510cccdea81b86bcb1b33e7be0cc2a Mon Sep 17 00:00:00 2001 From: whitequark Date: Sun, 25 Oct 2020 01:59:46 +0000 Subject: [PATCH] back.{verilog,rtlil}: adjust $verilog_initial_trigger insertion. To track upstream changes. --- nmigen/back/rtlil.py | 5 ++--- nmigen/back/verilog.py | 6 +++++- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index 05f219a..916605e 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -955,9 +955,8 @@ def _convert_fragment(builder, fragment, name_map, hierarchy): # simulators to work properly, and is universally ignored by synthesizers, # Verilator rejects it. # - # Running the Yosys proc_prune pass converts such pathological `always @*` - # blocks to `assign` statements, so this workaround can be removed completely - # once support for Yosys 0.9 is dropped. + # Yosys >=0.9+3468 emits a better workaround on its own, so this code can be + # removed completely once support for Yosys 0.9 is dropped. if not stmt_compiler._has_rhs: if verilog_trigger is None: verilog_trigger = \ diff --git a/nmigen/back/verilog.py b/nmigen/back/verilog.py index 37e4158..181a765 100644 --- a/nmigen/back/verilog.py +++ b/nmigen/back/verilog.py @@ -13,11 +13,15 @@ def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False, write_verilog script = [] script.append("read_ilang <= (0, 9, 3468): + # Yosys >=0.9+3468 (since commit 128522f1) emits the workaround for the `always @*` + # initial scheduling issue on its own. + script.append("delete w:$verilog_initial_trigger") + if yosys_version >= (0, 9, 3527): # Yosys >=0.9+3527 (since commit 656ee70f) supports the `-nomux` option for the `proc` # script pass. Because the individual `proc_*` passes are not a stable interface, # `proc -nomux` is used instead, if available. - script.append("delete w:$verilog_initial_trigger") script.append("proc -nomux") else: # On earlier versions, use individual `proc_*` passes; this is a known range of Yosys -- 2.30.2