From 3e22d4b9e610d792b75bfaf2e1da42f93d91d33a Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 7 Oct 2019 10:36:32 +0200
Subject: [PATCH] xilinx/common: be sure language is not vhdl when yosys
 synthesis is used

---
 litex/build/xilinx/common.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py
index 9ddc165e..1b3f052b 100644
--- a/litex/build/xilinx/common.py
+++ b/litex/build/xilinx/common.py
@@ -241,6 +241,7 @@ def _run_yosys(device, sources, vincpaths, build_name):
     for path in vincpaths:
         incflags += " -I" + path
     for filename, language, library in sources:
+        assert language != "vhdl"
         ys_contents += "read_{}{} {}\n".format(language, incflags, filename)
 
     ys_contents += """\
-- 
2.30.2