From 3e25f96dffba9a2a6ca220bbb03bd6f4631babc8 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Thu, 4 Feb 2021 20:26:51 +0100 Subject: [PATCH] update test_issuer_mmu_data_path.py to handle SPRs --- src/soc/fu/mmu/test/test_issuer_mmu_data_path.py | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py b/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py index f6208229..9d1836e5 100644 --- a/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py +++ b/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py @@ -17,12 +17,11 @@ class MMUTestCase(TestAccumulatorBase): lst = [ "dcbz 1,2", "tlbie 0,0,0,0,0", # RB,RS,RIC,PRS,R - #"mfspr 1, 18", # DSISR to reg 1 - #"mfspr 2, 19", # DAR to reg 2 - #"mtspr 18, 1", # TODO - #"mtspr 19, 2", # TODO - #"std 1, 0(2)" - "lhz 3, 0(1)" # load some data + "mtspr 18, 1", # reg 1 to DSISR + "mtspr 19, 2", # reg 2 to DAR + "mfspr 1, 18", # DSISR to reg 1 + "mfspr 2, 19", # DAR to reg 2 + "lhz 3, 0(1)" # load some data ] initial_regs = [0] * 32 -- 2.30.2