From 3e368593eb22d16de60c44ea721ca146082d3472 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 9 Apr 2019 14:33:37 -0700 Subject: [PATCH] Add cells.lut to techlibs/xilinx/ --- techlibs/xilinx/Makefile.inc | 1 + techlibs/xilinx/cells.lut | 15 +++++++++++++++ 2 files changed, 16 insertions(+) create mode 100644 techlibs/xilinx/cells.lut diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 9937c0c9c..432bb0770 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -31,6 +31,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.box)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.lut)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh)) diff --git a/techlibs/xilinx/cells.lut b/techlibs/xilinx/cells.lut new file mode 100644 index 000000000..3f3b69a8e --- /dev/null +++ b/techlibs/xilinx/cells.lut @@ -0,0 +1,15 @@ +# Max delays from https://pastebin.com/v2hrcksd +# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321 + +# Since LUT delays are pushed onto the fabric as routing delays, +# assume each input costs +100ps + +# K area delay +1 11 224 +2 12 224 324 +3 13 224 324 424 +4 14 224 324 424 524 +5 15 224 324 424 524 624 +6 20 224 324 424 524 624 724 +7 40 224 324 424 524 624 724 1020 +8 80 224 324 424 524 624 724 1020 1293 -- 2.30.2