From 3e5c062e96c11a6eaef1cbf94b5992391a850dbf Mon Sep 17 00:00:00 2001 From: Wilco Dijkstra Date: Fri, 6 Mar 2020 18:19:46 +0000 Subject: [PATCH] [AArch64] Fix lane specifier syntax The syntax for lane specifiers uses a vector element rather than a vector: fmls v0.2s, v1.2s, v1.s[1] // rather than v1.2s[1] Fix all the lane specifiers to use Vetype which uses the correct element type. gcc/ * aarch64/aarch64-simd.md (aarch64_mla_elt): Correct lane syntax. (aarch64_mla_elt_): Likewise. (aarch64_mls_elt): Likewise. (aarch64_mls_elt_): Likewise. (aarch64_fma4_elt): Likewise. (aarch64_fma4_elt_): Likewise. (aarch64_fma4_elt_to_64v2df): Likewise. (aarch64_fnma4_elt): Likewise. (aarch64_fnma4_elt_): Likewise. (aarch64_fnma4_elt_to_64v2df): Likewise. testsuite/ * gcc.target/aarch64/fmla_intrinsic_1.c: Check for correct lane syntax. * gcc.target/aarch64/fmls_intrinsic_1.c: Likewise. * gcc.target/aarch64/mla_intrinsic_1.c: Likewise. * gcc.target/aarch64/mls_intrinsic_1.c: Likewise. --- gcc/ChangeLog | 13 ++++++++++++ gcc/config/aarch64/aarch64-simd.md | 20 +++++++++---------- gcc/testsuite/ChangeLog | 7 +++++++ .../gcc.target/aarch64/fmla_intrinsic_1.c | 6 +++--- .../gcc.target/aarch64/fmls_intrinsic_1.c | 6 +++--- .../gcc.target/aarch64/mla_intrinsic_1.c | 4 ++-- .../gcc.target/aarch64/mls_intrinsic_1.c | 4 ++-- 7 files changed, 40 insertions(+), 20 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 957c4cc1c3b..1cb66942d40 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2020-03-06 Wilco Dijkstra + + * aarch64/aarch64-simd.md (aarch64_mla_elt): Correct lane syntax. + (aarch64_mla_elt_): Likewise. + (aarch64_mls_elt): Likewise. + (aarch64_mls_elt_): Likewise. + (aarch64_fma4_elt): Likewise. + (aarch64_fma4_elt_): Likewise. + (aarch64_fma4_elt_to_64v2df): Likewise. + (aarch64_fnma4_elt): Likewise. + (aarch64_fnma4_elt_): Likewise. + (aarch64_fnma4_elt_to_64v2df): Likewise. + 2020-03-06 Kyrylo Tkachov * config/aarch64/aarch64-sve2.md (@aarch64_sve_: diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 035f3163223..e5cf4e4549c 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1350,7 +1350,7 @@ "TARGET_SIMD" { operands[2] = aarch64_endian_lane_rtx (mode, INTVAL (operands[2])); - return "mla\t%0., %3., %1.[%2]"; + return "mla\t%0., %3., %1.[%2]"; } [(set_attr "type" "neon_mla__scalar")] ) @@ -1368,7 +1368,7 @@ "TARGET_SIMD" { operands[2] = aarch64_endian_lane_rtx (mode, INTVAL (operands[2])); - return "mla\t%0., %3., %1.[%2]"; + return "mla\t%0., %3., %1.[%2]"; } [(set_attr "type" "neon_mla__scalar")] ) @@ -1408,7 +1408,7 @@ "TARGET_SIMD" { operands[2] = aarch64_endian_lane_rtx (mode, INTVAL (operands[2])); - return "mls\t%0., %3., %1.[%2]"; + return "mls\t%0., %3., %1.[%2]"; } [(set_attr "type" "neon_mla__scalar")] ) @@ -1426,7 +1426,7 @@ "TARGET_SIMD" { operands[2] = aarch64_endian_lane_rtx (mode, INTVAL (operands[2])); - return "mls\t%0., %3., %1.[%2]"; + return "mls\t%0., %3., %1.[%2]"; } [(set_attr "type" "neon_mla__scalar")] ) @@ -2003,7 +2003,7 @@ "TARGET_SIMD" { operands[2] = aarch64_endian_lane_rtx (mode, INTVAL (operands[2])); - return "fmla\\t%0., %3., %1.[%2]"; + return "fmla\\t%0., %3., %1.[%2]"; } [(set_attr "type" "neon_fp_mla__scalar")] ) @@ -2020,7 +2020,7 @@ "TARGET_SIMD" { operands[2] = aarch64_endian_lane_rtx (mode, INTVAL (operands[2])); - return "fmla\\t%0., %3., %1.[%2]"; + return "fmla\\t%0., %3., %1.[%2]"; } [(set_attr "type" "neon_fp_mla__scalar")] ) @@ -2048,7 +2048,7 @@ "TARGET_SIMD" { operands[2] = aarch64_endian_lane_rtx (V2DFmode, INTVAL (operands[2])); - return "fmla\\t%0.2d, %3.2d, %1.2d[%2]"; + return "fmla\\t%0.2d, %3.2d, %1.d[%2]"; } [(set_attr "type" "neon_fp_mla_d_scalar_q")] ) @@ -2077,7 +2077,7 @@ "TARGET_SIMD" { operands[2] = aarch64_endian_lane_rtx (mode, INTVAL (operands[2])); - return "fmls\\t%0., %3., %1.[%2]"; + return "fmls\\t%0., %3., %1.[%2]"; } [(set_attr "type" "neon_fp_mla__scalar")] ) @@ -2095,7 +2095,7 @@ "TARGET_SIMD" { operands[2] = aarch64_endian_lane_rtx (mode, INTVAL (operands[2])); - return "fmls\\t%0., %3., %1.[%2]"; + return "fmls\\t%0., %3., %1.[%2]"; } [(set_attr "type" "neon_fp_mla__scalar")] ) @@ -2125,7 +2125,7 @@ "TARGET_SIMD" { operands[2] = aarch64_endian_lane_rtx (V2DFmode, INTVAL (operands[2])); - return "fmls\\t%0.2d, %3.2d, %1.2d[%2]"; + return "fmls\\t%0.2d, %3.2d, %1.d[%2]"; } [(set_attr "type" "neon_fp_mla_d_scalar_q")] ) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ea9bc42ff75..59c99885d54 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2020-03-06 Wilco Dijkstra + + * gcc.target/aarch64/fmla_intrinsic_1.c: Check for correct lane syntax. + * gcc.target/aarch64/fmls_intrinsic_1.c: Likewise. + * gcc.target/aarch64/mla_intrinsic_1.c: Likewise. + * gcc.target/aarch64/mls_intrinsic_1.c: Likewise. + 2020-03-06 Claudiu Zissulescu * gcc.target/arc/tumaddsidi4.c: Step-up optimization level. diff --git a/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c b/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c index 5b348827002..59ad41ed047 100644 --- a/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c +++ b/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c @@ -98,11 +98,11 @@ main (int argc, char **argv) /* vfma_laneq_f32. vfma_lane_f32. */ -/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s\\\[\[0-9\]+\\\]" 2 } } */ +/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */ /* vfmaq_lane_f32. vfmaq_laneq_f32. */ -/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 2 } } */ +/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */ /* vfma_lane_f64. */ /* { dg-final { scan-assembler-times "fmadd\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 1 } } */ @@ -110,6 +110,6 @@ main (int argc, char **argv) /* vfmaq_lane_f64. vfma_laneq_f64. vfmaq_laneq_f64. */ -/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2?d\\\[\[0-9\]+\\\]" 3 } } */ +/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 3 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c b/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c index 6c194a023d3..2d5a3d30536 100644 --- a/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c +++ b/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c @@ -99,11 +99,11 @@ main (int argc, char **argv) /* vfms_laneq_f32. vfms_lane_f32. */ -/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s\\\[\[0-9\]+\\\]" 2 } } */ +/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */ /* vfmsq_lane_f32. vfmsq_laneq_f32. */ -/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 2 } } */ +/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */ /* vfms_lane_f64. */ /* { dg-final { scan-assembler-times "fmsub\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 1 } } */ @@ -111,6 +111,6 @@ main (int argc, char **argv) /* vfmsq_lane_f64. vfms_laneq_f64. vfmsq_laneq_f64. */ -/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2?d\\\[\[0-9\]+\\\]" 3 } } */ +/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 3 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c b/gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c index 4bdfac76f40..46b3c78c131 100644 --- a/gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c +++ b/gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c @@ -78,6 +78,6 @@ main (int argc, char **argv) return 0; } -/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 4 } } */ -/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h\\\[\[0-9\]+\\\]" 4 } } */ +/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 4 } } */ +/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.h\\\[\[0-9\]+\\\]" 4 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c b/gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c index 4b13fafedcd..e01a4f6d0e1 100644 --- a/gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c +++ b/gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c @@ -83,6 +83,6 @@ main (int argc, char **argv) return 0; } -/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 4 } } */ -/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h\\\[\[0-9\]+\\\]" 4 } } */ +/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 4 } } */ +/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.h\\\[\[0-9\]+\\\]" 4 } } */ -- 2.30.2