From 3e6d3a54cc50c4b4b0b8757986b3baad458ebe6b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 3 Dec 2021 15:22:10 +0000 Subject: [PATCH] add misaligned ld/st to trigger an exception --- src/soc/simple/test/test_issuer_mmu.py | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/soc/simple/test/test_issuer_mmu.py b/src/soc/simple/test/test_issuer_mmu.py index 2076b7a0..e979c25f 100644 --- a/src/soc/simple/test/test_issuer_mmu.py +++ b/src/soc/simple/test/test_issuer_mmu.py @@ -115,6 +115,22 @@ class MMUTestCase(TestAccumulatorBase): self.add_case(Program(lst, bigendian), initial_regs, initial_mem=initial_mem,initial_msr=initial_msr) + # deliberately misalign + def case_6_ldst_misalign(self): + lst = ["std 10,0(2)"] + initial_regs = [0] * 32 + initial_regs[1] = 0x1234 + initial_regs[2] = 0x3456 + initial_regs[3] = 0x4321 + initial_regs[4] = 0x6543 + initial_regs[10] = 0x0123456789abcdef + initial_mem = {} + #enable virtmode + initial_msr = 1 << MSR.PR # must set "problem" state for virtual memory + print("MMUTEST: initial_msr=",initial_msr) + self.add_case(Program(lst, bigendian), initial_regs, + initial_mem=initial_mem,initial_msr=initial_msr) + if __name__ == "__main__": svp64 = True if len(sys.argv) == 2: -- 2.30.2