From 3e732797cdf087903b68c58e9cebcc89f054ab1e Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 18 Sep 2022 14:24:09 +0100 Subject: [PATCH] --- openpower/sv/cr_ops.mdwn | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn index 18c8d0319..f9008ab81 100644 --- a/openpower/sv/cr_ops.mdwn +++ b/openpower/sv/cr_ops.mdwn @@ -79,9 +79,7 @@ SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations: | 6 | 7 | 19-20 | 21 | 22 23 | description | | - | - |-------| --- |---------|----------------- | |sz |SNZ| 0 RG | 0 | dz / | simple mode | -|sz |SNZ| 0 RG | 1 | 0 / | scalar reduce mode (mapreduce), SUBVL=1 | -|zz |SNZ| 0 RG | 1 | SVM 0 | subvector reduce mode, SUBVL>1 | -|zz |SNZ| 0 RG | 1 | / 1 | reserved | +|sz |SNZ| 0 RG | 1 | 0 / | scalar reduce mode (mapreduce) | |zz |SNZ| 1 VLI | inv | CR-bit | Ffirst 3-bit mode | |sz |SNZ| 1 VLI | inv | dz / | Ffirst 5-bit mode | -- 2.30.2