From 3e77a18bc9e7782e2c79fb92ef041f82af13a7e7 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Sat, 26 Oct 2019 16:22:53 +0200 Subject: [PATCH] class decl cleanup --- absyn.py | 75 +++++++++++++++++++++++++++++++++++++ examples/assignment.sv | 2 +- examples/test_assignment.py | 22 +++++++++++ parse_sv.py | 70 ++-------------------------------- 4 files changed, 101 insertions(+), 68 deletions(-) create mode 100644 examples/test_assignment.py diff --git a/absyn.py b/absyn.py index c59f8b6..e121357 100644 --- a/absyn.py +++ b/absyn.py @@ -1,5 +1,80 @@ +from lib2to3.pytree import Node, Leaf +from lib2to3.pgen2 import token +from lib2to3.pygram import python_symbols as syms + +preamble = """# this file has been generated by sv2nmigen + +from nmigen import Signal, Module, Const, Cat, Elaboratable + + + +""" + +indent_debug = 0 + class Absyn: def __init__(self): self.outputfile = open("output.py","w") + self.outputfile.write(preamble) def printpy(self,p): self.outputfile.write(str(p)+"\n") + def assign(self,p): + p = list(p) + if(p[1]=="assign"): + self.printpy(p[4]) + # m.d.comb += [l.eq(r)] + def indent(self,count): + if(indent_debug): + return Leaf(token.INDENT, '>>> '*count) + else: + return Leaf(token.INDENT, ' '*4*count) + + def dedent(self,count): + return Leaf(token.DEDENT, '') + def nl(self): + return Leaf(token.NEWLINE, '#\n') + + def initPorts(self,params,ports): + pass_stmt = Node(syms.pass_stmt ,[Leaf(token.NAME, "def __init__(self):")]) + if params: + params = [Leaf(token.LPAR, '(')] + params + [Leaf(token.RPAR, ')')] + fn = [Leaf(token.NAME, 'def'), + Leaf(token.NAME, '__initXXX__', prefix=' '), + Node(syms.parameters, params), + Leaf(token.COLON, ':')] + fndef = Node(syms.funcdef, fn) + stmts = Node(syms.stmt, [fndef]) + else: + stmts = Node(syms.small_stmt, [pass_stmt, Leaf(token.NEWLINE, '\n')]) + stmts = Node(syms.stmt, [stmts]) + + for port in ports: + stmts.children.append(self.indent(2)) + stmts.children.append(port) + stmts.children.append(self.nl()) + + return stmts + + + def module_1(self,p): + params = p[7] + ports = p[8] + clsname = [Leaf(token.NAME, 'class'), + Leaf(token.NAME, p[4], prefix=' '), + Leaf(token.LPAR,'('), + Leaf(token.NAME, 'Elaboratable'), + Leaf(token.LPAR,')'), + Leaf(token.COLON, ':'), + ] + + suite = Node(syms.suite, [Leaf(token.NEWLINE, '\n'), + self.indent(1), + self.initPorts(params,ports), + self.dedent(1) + ]) + clsdecl = Node(syms.classdef, clsname + [suite]) + clsdecl = Node(syms.compound_stmt, [clsdecl]) + #.printpy("#clsdecl"+ repr(clsdecl)) + #absyn.printpy("#clsstr:") + self.printpy(str(clsdecl)) + return clsdecl diff --git a/examples/assignment.sv b/examples/assignment.sv index 73483f7..e3e326e 100644 --- a/examples/assignment.sv +++ b/examples/assignment.sv @@ -1,4 +1,4 @@ -module up_counter( +module assignment( input i, output o ); diff --git a/examples/test_assignment.py b/examples/test_assignment.py new file mode 100644 index 0000000..3972ac4 --- /dev/null +++ b/examples/test_assignment.py @@ -0,0 +1,22 @@ +from nmigen.compat.sim import run_simulation + +import assignment + +def tbench(dut): + yield dut.i.eq(1) + yield + yield + yield + yield dut.i.eq(0) + yield + yield + yield + + +def test_ass(): + dut = assignment.assignment(); + run_simulation(dut, tbench(dut), vcd_name="test.vcd") + + +if __name__ == "__main__": + test_ass() diff --git a/parse_sv.py b/parse_sv.py index 0c6ad9c..627aa03 100644 --- a/parse_sv.py +++ b/parse_sv.py @@ -101,7 +101,7 @@ NP_POUTPUT = 'POUTPUT' NP_PINOUT = 'PINOUT' NP_PREF = 'PREF' -indent = ' ' + class DataType: @@ -4709,7 +4709,7 @@ def p_list_of_port_declarations_1(p): def p_list_of_port_declarations_2(p): '''list_of_port_declarations : list_of_port_declarations ',' port_declaration ''' if(parse_debug): print('list_of_port_declarations_2 FIXME', list(p)) - p[1].append(Leaf(token.NEWLINE, '\n')) # should be a comma + # MOVE_TO absyn p[1].append(Leaf(token.NEWLINE, '\n')) # should be a comma # XXX p[3].prefix=' ' # add a space after the NL, must go in parameter p[1].append(p[3]) p[0] = p[1] @@ -5043,72 +5043,8 @@ def p_cont_assign_list_2(p): def p_module_1(p): '''module : attribute_list_opt module_start lifetime_opt IDENTIFIER _embed0_module module_package_import_list_opt module_parameter_port_list_opt module_port_list_opt module_attribute_foreign ';' _embed1_module timeunits_declaration_opt _embed2_module module_item_list_opt module_end _embed3_module endlabel_opt ''' if(parse_debug>2): print('module_1', list(p)) - absyn.printpy("# module_1") - params = p[7] - clsname = [Leaf(token.NAME, 'class'), - Leaf(token.NAME, p[4], prefix=' '), - Leaf(token.COLON, ':')] - pass_stmt = Node(syms.pass_stmt, [Leaf(token.NAME, "pass"),]) - if params: - params = [Leaf(token.LPAR, '(')] + params + [Leaf(token.RPAR, ')')] - fn = [Leaf(token.NAME, 'def'), - Leaf(token.NAME, '__init__', prefix=' '), - Node(syms.parameters, params), - Leaf(token.COLON, ':')] - fndef = Node(syms.funcdef, fn) - stmts = Node(syms.stmt, [fndef]) - else: - stmts = Node(syms.small_stmt, [pass_stmt, Leaf(token.NEWLINE, '\n')]) - stmts = Node(syms.stmt, [stmts]) - - ports = p[8] - for port in ports: - stmts.children.append(Leaf(token.INDENT, indent*2)) - stmts.children.append(Leaf(token.STRING, port)) - - suite = Node(syms.suite, [Leaf(token.NEWLINE, '\n'), - Leaf(token.INDENT, ' '), - stmts, - Leaf(token.DEDENT, '') - ]) - clsdecl = Node(syms.classdef, clsname + [suite]) - clsdecl = Node(syms.compound_stmt, [clsdecl]) - absyn.printpy("#clsdecl"+ repr(clsdecl)) - absyn.printpy("#clsstr:") - absyn.printpy(str(clsdecl)) + clsdecl = absyn.module_1(p) p[0] = clsdecl - # { // Last step: check any closing name. This is done late so - # // that the parser can look ahead to detect the present - # // endlabel_opt but still have the pform_endmodule() called - # // early enough that the lexor can know we are outside the - # // module. - # if (p[1]7) { - # if (strcmp(p[4],p[1]7) != 0) { - # switch (p[2]) { - # case K_module: - # yyerror(@17, "error: End label doesn't match " - # "module name."); - # break; - # case K_program: - # yyerror(@17, "error: End label doesn't match " - # "program name."); - # break; - # case K_interface: - # yyerror(@17, "error: End label doesn't match " - # "interface name."); - # break; - # default: - # break; - # } - # } - # if ((p[2] == K_module) && (! gn_system_verilog())) { - # yyerror(@8, "error: Module end labels require " - # "SystemVerilog."); - # } - # delete[]p[1]7; - # } - # delete[]p[4]; - # } () def p__embed0_module(p): '''_embed0_module : ''' -- 2.30.2