From 3e7a87f17c00b67c19765c2e76243848c9124ca1 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 26 Dec 2020 23:28:15 +0000 Subject: [PATCH] --- openpower/sv/svp64.mdwn | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index a76257921..e5f346da0 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -37,13 +37,14 @@ svp64 fits into the "reserved" portions of the v3.1B prefix, making it possible ## SVP64 encoding features -A number of features need to be compacted into a very small space: +A number of features need to be compacted into a very small space of only 24 bits: -* Scalar/Vector tagging and range extension on every register +* Independent per-register Scalar/Vector tagging and range extension on every register * Element width overrides on both source and destination * Predication on both source and destination * Two different *types* of predication: INT and CR -* SV Modes including saturation (for A/V DSP), mapreduce, fail-first and more. +* SV Modes including saturation (for A/V DSP), mapreduce, fail-first and + predicate-result mode. This document focusses specifically on how that fits into available space. The [[svp64/appendix]] explains more of the details, whilst the [[sv/overview]] gives the basics. -- 2.30.2