From 3e89c56468a5f6e46f894180d1f0a5242f944f10 Mon Sep 17 00:00:00 2001 From: Mateusz Holenko Date: Tue, 23 Jul 2019 11:48:00 +0200 Subject: [PATCH] cpu/vexriscv: bump submodule --- litex/soc/cores/cpu/vexriscv/verilog | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog index 03f7f9d4..747a2e01 160000 --- a/litex/soc/cores/cpu/vexriscv/verilog +++ b/litex/soc/cores/cpu/vexriscv/verilog @@ -1 +1 @@ -Subproject commit 03f7f9d46c9c862e1ef3ebbe19b5113b882e4358 +Subproject commit 747a2e012f43d13c3487acc3c758477aad277559 -- 2.30.2