From 3ea35b8566e4fe6b0ba24fb61257c6667cdbbf17 Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 27 Dec 2018 21:45:55 +0000 Subject: [PATCH] lib.coding: fix tests to actually run, and fix code to fix tests. --- nmigen/lib/coding.py | 7 +++---- nmigen/test/test_lib_coding.py | 17 ++++++++++------- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/nmigen/lib/coding.py b/nmigen/lib/coding.py index 6509077..f9c2c63 100644 --- a/nmigen/lib/coding.py +++ b/nmigen/lib/coding.py @@ -69,7 +69,7 @@ class PriorityEncoder: m = Module() for j, b in enumerate(reversed(self.i)): with m.If(b): - m.d.comb += self.o.eq(j) + m.d.comb += self.o.eq(len(self.i) - j - 1) m.d.comb += self.n.eq(self.i == 0) return m.lower(platform) @@ -105,9 +105,8 @@ class Decoder: for j in range(len(self.o)): with m.Case(j): m.d.comb += self.o.eq(1 << j) - with m.Case(): - with m.If(self.n): - m.d.comb += self.o.eq(0) + with m.If(self.n): + m.d.comb += self.o.eq(0) return m.lower(platform) diff --git a/nmigen/test/test_lib_coding.py b/nmigen/test/test_lib_coding.py index 5569e76..c535c79 100644 --- a/nmigen/test/test_lib_coding.py +++ b/nmigen/test/test_lib_coding.py @@ -28,6 +28,7 @@ class EncoderTestCase(FHDLTestCase): self.assertEqual((yield enc.o), 0) sim.add_process(process) + sim.run() class PriorityEncoderTestCase(FHDLTestCase): @@ -54,6 +55,7 @@ class PriorityEncoderTestCase(FHDLTestCase): self.assertEqual((yield enc.o), 1) sim.add_process(process) + sim.run() class DecoderTestCase(FHDLTestCase): @@ -61,18 +63,19 @@ class DecoderTestCase(FHDLTestCase): dec = Decoder(4) with Simulator(dec) as sim: def process(): - self.assertEqual((yield enc.o), 0b0001) + self.assertEqual((yield dec.o), 0b0001) - yield enc.i.eq(1) + yield dec.i.eq(1) yield Delay() - self.assertEqual((yield enc.o), 0b0010) + self.assertEqual((yield dec.o), 0b0010) - yield enc.i.eq(3) + yield dec.i.eq(3) yield Delay() - self.assertEqual((yield enc.o), 0b1000) + self.assertEqual((yield dec.o), 0b1000) - yield enc.n.eq(1) + yield dec.n.eq(1) yield Delay() - self.assertEqual((yield enc.o), 0b0000) + self.assertEqual((yield dec.o), 0b0000) sim.add_process(process) + sim.run() -- 2.30.2