From 3ebbeba6d5daa236ff346f313e79a9359d1a37bd Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU>
Date: Thu, 11 Nov 2010 15:49:21 -0800
Subject: [PATCH] [sim] handle integer division overflow

Behavior is now same as GCC's optimizer.  Previously, we just crashed :)
---
 riscv/insns/div.h   | 5 ++++-
 riscv/insns/divu.h  | 5 ++++-
 riscv/insns/divuw.h | 6 ++++--
 riscv/insns/divw.h  | 6 ++++--
 riscv/insns/rem.h   | 5 ++++-
 riscv/insns/remu.h  | 5 ++++-
 riscv/insns/remuw.h | 6 ++++--
 riscv/insns/remw.h  | 6 ++++--
 8 files changed, 32 insertions(+), 12 deletions(-)

diff --git a/riscv/insns/div.h b/riscv/insns/div.h
index 9b752aa..f6a9b6b 100644
--- a/riscv/insns/div.h
+++ b/riscv/insns/div.h
@@ -1,2 +1,5 @@
 require64;
-RD = sreg_t(RS1) / sreg_t(RS2);
+if(RS2 == 0 || sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1)
+  RD = sreg_t(RS1) < 0 ? INT64_MIN : INT64_MAX;
+else
+  RD = sreg_t(RS1) / sreg_t(RS2);
diff --git a/riscv/insns/divu.h b/riscv/insns/divu.h
index f1b65fd..86792a2 100644
--- a/riscv/insns/divu.h
+++ b/riscv/insns/divu.h
@@ -1,2 +1,5 @@
 require64;
-RD = RS1 / RS2;
+if(RS2 == 0)
+  RD = UINT64_MAX;
+else
+  RD = RS1 / RS2;
diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h
index 46f7814..296bb9e 100644
--- a/riscv/insns/divuw.h
+++ b/riscv/insns/divuw.h
@@ -1,2 +1,4 @@
-RD = sext32(uint32_t(RS1)/uint32_t(RS2));
-
+if(uint32_t(RS2) == 0)
+  RD = sext32(UINT32_MAX);
+else
+  RD = sext32(uint32_t(RS1)/uint32_t(RS2));
diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h
index 0654b49..0537469 100644
--- a/riscv/insns/divw.h
+++ b/riscv/insns/divw.h
@@ -1,2 +1,4 @@
-RD = sext32(int32_t(RS1)/int32_t(RS2));
-
+if(int32_t(RS2) == 0 || int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1)
+  RD = sext32(int32_t(RS1) < 0 ? INT32_MIN : INT32_MAX);
+else
+  RD = sext32(int32_t(RS1)/int32_t(RS2));
diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h
index 1c82b95..146dbc6 100644
--- a/riscv/insns/rem.h
+++ b/riscv/insns/rem.h
@@ -1,2 +1,5 @@
 require64;
-RD = sreg_t(RS1) % sreg_t(RS2);
+if(RS2 == 0 || sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1)
+  RD = 0;
+else
+  RD = sreg_t(RS1) % sreg_t(RS2);
diff --git a/riscv/insns/remu.h b/riscv/insns/remu.h
index e6af512..3b6c44f 100644
--- a/riscv/insns/remu.h
+++ b/riscv/insns/remu.h
@@ -1,2 +1,5 @@
 require64;
-RD = RS1 % RS2;
+if(RS2 == 0)
+  RD = 0;
+else
+  RD = RS1 % RS2;
diff --git a/riscv/insns/remuw.h b/riscv/insns/remuw.h
index 0a7a1ba..820a396 100644
--- a/riscv/insns/remuw.h
+++ b/riscv/insns/remuw.h
@@ -1,2 +1,4 @@
-RD = sext32(uint32_t(RS1) % uint32_t(RS2));
-
+if(uint32_t(RS2) == 0)
+  RD = 0;
+else
+  RD = sext32(uint32_t(RS1) % uint32_t(RS2));
diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h
index 0d67c88..0e68dc6 100644
--- a/riscv/insns/remw.h
+++ b/riscv/insns/remw.h
@@ -1,2 +1,4 @@
-RD = sext32(int32_t(RS1) % int32_t(RS2));
-
+if(int32_t(RS2) == 0 || int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1)
+  RD = 0;
+else
+  RD = sext32(int32_t(RS1) % int32_t(RS2));
-- 
2.30.2