From 3ebf4143be6523a59f9be398a0c51134ae64f4e3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 11 Apr 2020 09:53:51 +0100 Subject: [PATCH] adding immediates, tracking down a bug --- src/soc/experiment/score6600.py | 10 +++++++--- src/soc/experiment/sim.py | 1 + 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/src/soc/experiment/score6600.py b/src/soc/experiment/score6600.py index 2fe8c408..2e7602ca 100644 --- a/src/soc/experiment/score6600.py +++ b/src/soc/experiment/score6600.py @@ -1104,13 +1104,16 @@ def scoreboard_sim(dut, alusim): instrs.append((7, 6, 6, 2, 0, 0, (0, 0))) instrs.append((1, 7, 2, 2, 0, 0, (0, 0))) - if True: + if False: instrs.append((2, 3, 3, InternalOp.OP_ADD, Function.ALU, 0, 0, (0, 0))) instrs.append((5, 3, 3, InternalOp.OP_ADD, Function.ALU, 0, 0, (0, 0))) if True: instrs.append((3, 5, 5, InternalOp.OP_MUL_L64, Function.ALU, + 1, 7, (0, 0))) + if False: + instrs.append((2, 3, 3, InternalOp.OP_ADD, Function.ALU, 0, 0, (0, 0))) if False: @@ -1232,8 +1235,9 @@ def scoreboard_sim(dut, alusim): def test_scoreboard(): - dut = IssueToScoreboard(2, 1, 1, 16, 8, 8) - alusim = RegSim(16, 8) + regwidth = 64 + dut = IssueToScoreboard(2, 1, 1, regwidth, 8, 8) + alusim = RegSim(regwidth, 8) memsim = MemSim(16, 8) vl = rtlil.convert(dut, ports=dut.ports()) with open("test_scoreboard6600.il", "w") as f: diff --git a/src/soc/experiment/sim.py b/src/soc/experiment/sim.py index 66b37ee8..a96f90a8 100644 --- a/src/soc/experiment/sim.py +++ b/src/soc/experiment/sim.py @@ -46,6 +46,7 @@ class RegSim: val = src1 + src2 elif op == InternalOp.OP_MUL_L64: val = src1 * src2 + print ("mul src1, src2", src1, src2, val) elif op == ISUB: val = src1 - src2 elif op == ISHF: -- 2.30.2