From 3ec1be97aca4a9707c6a368b406353ac49e494cc Mon Sep 17 00:00:00 2001 From: Charles Baylis Date: Fri, 24 Oct 2014 14:58:51 +0000 Subject: [PATCH] [PATCH 1/2] [AARCH64,NEON] Add patterns + builtins for vld[234](q?)_lane_* intrinsics 2014-10-24 Charles Baylis * config/aarch64/aarch64-builtins.c (aarch64_types_loadstruct_lane_qualifiers): Define. * config/aarch64/aarch64-simd-builtins.def (ld2_lane, ld3_lane, ld4_lane): New builtins. * config/aarch64/aarch64-simd.md (aarch64_vec_load_lanesoi_lane): New pattern. (aarch64_vec_load_lanesci_lane): Likewise. (aarch64_vec_load_lanesxi_lane): Likewise. (aarch64_ld2_lane): New expand. (aarch64_ld3_lane): Likewise. (aarch64_ld4_lane): Likewise. * config/aarch64/aarch64.md (define_c_enum "unspec"): Add UNSPEC_LD2_LANE, UNSPEC_LD3_LANE, UNSPEC_LD4_LANE. From-SVN: r216671 --- gcc/ChangeLog | 17 ++++ gcc/config/aarch64/aarch64-builtins.c | 5 ++ gcc/config/aarch64/aarch64-simd-builtins.def | 4 + gcc/config/aarch64/aarch64-simd.md | 95 ++++++++++++++++++++ gcc/config/aarch64/aarch64.md | 3 + 5 files changed, 124 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8863eb68531..698944c527d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,20 @@ +2014-10-24 Charles Baylis + * config/aarch64/aarch64-builtins.c + (aarch64_types_loadstruct_lane_qualifiers): Define. + * config/aarch64/aarch64-simd-builtins.def (ld2_lane, ld3_lane, + ld4_lane): New builtins. + * config/aarch64/aarch64-simd.md (aarch64_vec_load_lanesoi_lane): + New pattern. + (aarch64_vec_load_lanesci_lane): Likewise. + (aarch64_vec_load_lanesxi_lane): Likewise. + (aarch64_ld2_lane): New expand. + (aarch64_ld3_lane): Likewise. + (aarch64_ld4_lane): Likewise. + * config/aarch64/aarch64.md (define_c_enum "unspec"): Add + UNSPEC_LD2_LANE, UNSPEC_LD3_LANE, UNSPEC_LD4_LANE. + +Change-Id: I4c36d18072215133573e07483cfe12165201c339 + 2014-10-24 Georg-Johann Lay * avr-protos.h (avr_out_sign_extend): New. diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index 3dba1b29875..368d3a76bc3 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -201,6 +201,11 @@ aarch64_types_load1_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_const_pointer_map_mode }; #define TYPES_LOAD1 (aarch64_types_load1_qualifiers) #define TYPES_LOADSTRUCT (aarch64_types_load1_qualifiers) +static enum aarch64_type_qualifiers +aarch64_types_loadstruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_const_pointer_map_mode, + qualifier_none, qualifier_none }; +#define TYPES_LOADSTRUCT_LANE (aarch64_types_loadstruct_lane_qualifiers) static enum aarch64_type_qualifiers aarch64_types_bsl_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index ace5ebe0b7b..5d0e7d8a714 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -87,6 +87,10 @@ BUILTIN_VALLDIF (LOADSTRUCT, ld2r, 0) BUILTIN_VALLDIF (LOADSTRUCT, ld3r, 0) BUILTIN_VALLDIF (LOADSTRUCT, ld4r, 0) + /* Implemented by aarch64_ld_lane. */ + BUILTIN_VQ (LOADSTRUCT_LANE, ld2_lane, 0) + BUILTIN_VQ (LOADSTRUCT_LANE, ld3_lane, 0) + BUILTIN_VQ (LOADSTRUCT_LANE, ld4_lane, 0) /* Implemented by aarch64_st. */ BUILTIN_VDC (STORESTRUCT, st2, 0) BUILTIN_VDC (STORESTRUCT, st3, 0) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index da576a57154..b260bc62a2f 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4001,6 +4001,18 @@ [(set_attr "type" "neon_load2_all_lanes")] ) +(define_insn "aarch64_vec_load_lanesoi_lane" + [(set (match_operand:OI 0 "register_operand" "=w") + (unspec:OI [(match_operand: 1 "aarch64_simd_struct_operand" "Utv") + (match_operand:OI 2 "register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ] + UNSPEC_LD2_LANE))] + "TARGET_SIMD" + "ld2\\t{%S0. - %T0.}[%3], %1" + [(set_attr "type" "neon_load2_one_lane")] +) + (define_insn "vec_store_lanesoi" [(set (match_operand:OI 0 "aarch64_simd_struct_operand" "=Utv") (unspec:OI [(match_operand:OI 1 "register_operand" "w") @@ -4042,6 +4054,18 @@ [(set_attr "type" "neon_load3_all_lanes")] ) +(define_insn "aarch64_vec_load_lanesci_lane" + [(set (match_operand:CI 0 "register_operand" "=w") + (unspec:CI [(match_operand: 1 "aarch64_simd_struct_operand" "Utv") + (match_operand:CI 2 "register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_LD3_LANE))] + "TARGET_SIMD" + "ld3\\t{%S0. - %U0.}[%3], %1" + [(set_attr "type" "neon_load3_one_lane")] +) + (define_insn "vec_store_lanesci" [(set (match_operand:CI 0 "aarch64_simd_struct_operand" "=Utv") (unspec:CI [(match_operand:CI 1 "register_operand" "w") @@ -4083,6 +4107,18 @@ [(set_attr "type" "neon_load4_all_lanes")] ) +(define_insn "aarch64_vec_load_lanesxi_lane" + [(set (match_operand:XI 0 "register_operand" "=w") + (unspec:XI [(match_operand: 1 "aarch64_simd_struct_operand" "Utv") + (match_operand:XI 2 "register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_LD4_LANE))] + "TARGET_SIMD" + "ld4\\t{%S0. - %V0.}[%3], %1" + [(set_attr "type" "neon_load4_one_lane")] +) + (define_insn "vec_store_lanesxi" [(set (match_operand:XI 0 "aarch64_simd_struct_operand" "=Utv") (unspec:XI [(match_operand:XI 1 "register_operand" "w") @@ -4435,6 +4471,65 @@ DONE; }) +(define_expand "aarch64_ld2_lane" + [(match_operand:OI 0 "register_operand" "=w") + (match_operand:DI 1 "register_operand" "w") + (match_operand:OI 2 "register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + "TARGET_SIMD" +{ + enum machine_mode mode = mode; + rtx mem = gen_rtx_MEM (mode, operands[1]); + + aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); + emit_insn (gen_aarch64_vec_load_lanesoi_lane (operands[0], + mem, + operands[2], + operands[3])); + DONE; +}) + +(define_expand "aarch64_ld3_lane" + [(match_operand:CI 0 "register_operand" "=w") + (match_operand:DI 1 "register_operand" "w") + (match_operand:CI 2 "register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + "TARGET_SIMD" +{ + enum machine_mode mode = mode; + rtx mem = gen_rtx_MEM (mode, operands[1]); + + aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); + emit_insn (gen_aarch64_vec_load_lanesci_lane (operands[0], + mem, + operands[2], + operands[3])); + DONE; +}) + +(define_expand "aarch64_ld4_lane" + [(match_operand:XI 0 "register_operand" "=w") + (match_operand:DI 1 "register_operand" "w") + (match_operand:XI 2 "register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + "TARGET_SIMD" +{ + enum machine_mode mode = mode; + rtx mem = gen_rtx_MEM (mode, operands[1]); + + aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); + emit_insn (gen_aarch64_vec_load_lanesxi_lane (operands[0], + mem, + operands[2], + operands[3])); + DONE; +}) + + + ;; Expanders for builtins to extract vector registers from large ;; opaque integer modes. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index cda69791cdb..341c26f42d8 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -95,6 +95,9 @@ UNSPEC_LD3_DUP UNSPEC_LD4 UNSPEC_LD4_DUP + UNSPEC_LD2_LANE + UNSPEC_LD3_LANE + UNSPEC_LD4_LANE UNSPEC_MB UNSPEC_NOP UNSPEC_PRLG_STK -- 2.30.2