From 3eca19ea830b6c9948bb1c9563f1f101ac5d28b5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 9 May 2021 15:34:55 +0100 Subject: [PATCH] update code-comments --- src/soc/experiment/pimem.py | 3 ++- src/soc/fu/ldst/loadstore.py | 10 ++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py index b051edd1..51772073 100644 --- a/src/soc/experiment/pimem.py +++ b/src/soc/experiment/pimem.py @@ -12,6 +12,7 @@ Links: * https://bugs.libre-soc.org/show_bug.cgi?id=216 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/ +* https://bugs.libre-soc.org/show_bug.cgi?id=465 - exception handling """ @@ -296,7 +297,7 @@ class PortInterfaceBase(Elaboratable): comb += adrok_l.r.eq(1) # address reset comb += st_done.r.eq(1) # store done reset - # monitor for an exception or the completion of LD. + # monitor for an exception, clear busy immediately with m.If(self.pi.exc_o.happened): comb += busy_l.r.eq(1) diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py index 5c43ebc6..0397f87d 100644 --- a/src/soc/fu/ldst/loadstore.py +++ b/src/soc/fu/ldst/loadstore.py @@ -1,3 +1,13 @@ +"""LoadStore1 FSM. + +based on microwatt loadstore1.vhdl + +Links: + +* https://bugs.libre-soc.org/show_bug.cgi?id=465 + +""" + from nmigen import (Elaboratable, Module, Signal, Shape, unsigned, Cat, Mux, Record, Memory, Const) -- 2.30.2