From 3ed9f8fba38b54c70fffc50318bec1cb7c36c131 Mon Sep 17 00:00:00 2001 From: Xan Date: Wed, 25 Apr 2018 12:03:34 +0100 Subject: [PATCH] --- ...alysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn index 03a1d9b03..74d4a8a4d 100644 --- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn +++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn @@ -2,7 +2,7 @@ ## Register file -The default Harmonised RVP GPR register file is divided into a lower bank of Vector[INT8] and an upper bank of Vector[INT16] +The default Harmonised RVP GPR register file is divided into a lower bank of Vector[INT8] and an upper bank of Vector[INT16]. In contrast, the Andes Packed SIMD ISA permits any GPR to be used for either INT8 or INT16 vector operations | Register | Andes ISA | Harmonised RVP ISA | -- 2.30.2