From 3edfacea9c30b0f1c38c3296e7e4110251a247a5 Mon Sep 17 00:00:00 2001 From: Ciro Santilli Date: Tue, 27 Aug 2019 15:17:24 +0100 Subject: [PATCH] cpu: reset byte_enable across writeMem calls data_write_req byteEnable which is used in ARM SVE partial writes was not being zeroed between writes. As a result, non-SVE memory write instructions such as STP that followed SVE memory write instructions could still have the write mask active. This could lead to wrong simulation behaviour, and to an assertion failure: src/mem/packet.hh:1211: void Packet::writeData(uint8_t*) const: Assertion `req->getByteEnable().size() == getSize()' failed. '` Change-Id: I74b5a82675e9923b0ffdf2c1dd9afb00c91cb204 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20448 Reviewed-by: Jason Lowe-Power Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg Tested-by: kokoro --- src/cpu/simple/atomic.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index aa2b64112..a873e6de7 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -1,6 +1,6 @@ /* * Copyright 2014 Google, Inc. - * Copyright (c) 2012-2013,2015,2017-2018 ARM Limited + * Copyright (c) 2012-2013,2015,2017-2019 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -362,6 +362,7 @@ AtomicSimpleCPU::genMemFragmentRequest(const RequestPtr& req, Addr frag_addr, } else { req->setVirt(0, frag_addr, frag_size, flags, dataMasterId(), inst_addr); + req->setByteEnable(std::vector()); } return predicate; -- 2.30.2