From 3ee3ad561a29d5429309571db489f95e4ccaec5b Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Mon, 27 Apr 2020 21:17:56 +0100 Subject: [PATCH] aco: fix vgpr nir_op_vecn with sgpr operands MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Rhys Perry Reviewed-by: Daniel Schürmann Part-of: --- src/amd/compiler/aco_instruction_selection.cpp | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 0732a2017d9..beaebdb1257 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -1017,8 +1017,13 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) if (instr->dest.dest.ssa.bit_size >= 32 || dst.type() == RegType::vgpr) { aco_ptr vec{create_instruction(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.dest.ssa.num_components, 1)}; - for (unsigned i = 0; i < num; ++i) - vec->operands[i] = Operand{elems[i]}; + RegClass elem_rc = RegClass::get(RegType::vgpr, instr->dest.dest.ssa.bit_size / 8u); + for (unsigned i = 0; i < num; ++i) { + if (elems[i].type() == RegType::sgpr && elem_rc.is_subdword()) + vec->operands[i] = Operand(emit_extract_vector(ctx, elems[i], 0, elem_rc)); + else + vec->operands[i] = Operand{elems[i]}; + } vec->definitions[0] = Definition(dst); ctx->block->instructions.emplace_back(std::move(vec)); ctx->allocated_vec.emplace(dst.id(), elems); -- 2.30.2