From 3eed59768c39c6faeb1be0f3bc0bb283656c1f90 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 19 Apr 2009 03:47:59 -0700 Subject: [PATCH] X86: Explicitly use the right width in a few places that need a 64 bit value. --- .../general_purpose/flags/set_and_clear.py | 8 +++--- .../isa/insts/general_purpose/system_calls.py | 28 +++++++++---------- src/arch/x86/isa/insts/romutil.py | 4 +-- src/arch/x86/isa/insts/system/segmentation.py | 12 ++++---- 4 files changed, 26 insertions(+), 26 deletions(-) diff --git a/src/arch/x86/isa/insts/general_purpose/flags/set_and_clear.py b/src/arch/x86/isa/insts/general_purpose/flags/set_and_clear.py index e151dc61d..cfd90638b 100644 --- a/src/arch/x86/isa/insts/general_purpose/flags/set_and_clear.py +++ b/src/arch/x86/isa/insts/general_purpose/flags/set_and_clear.py @@ -56,14 +56,14 @@ microcode = ''' def macroop CLD { ruflags t1 - limm t2, "~((uint64_t)DFBit)" + limm t2, "~((uint64_t)DFBit)", dataSize=8 and t1, t1, t2 wruflags t1, t0 }; def macroop STD { ruflags t1 - limm t2, "DFBit" + limm t2, "DFBit", dataSize=8 or t1, t1, t2 wruflags t1, t0 }; @@ -87,14 +87,14 @@ def macroop CMC { def macroop STI { rflags t1 - limm t2, "IFBit" + limm t2, "IFBit", dataSize=8 or t1, t1, t2 wrflags t1, t0 }; def macroop CLI { rflags t1 - limm t2, "~IFBit" + limm t2, "~IFBit", dataSize=8 and t1, t1, t2 wrflags t1, t0 }; diff --git a/src/arch/x86/isa/insts/general_purpose/system_calls.py b/src/arch/x86/isa/insts/general_purpose/system_calls.py index 67607d5f8..fb282502d 100644 --- a/src/arch/x86/isa/insts/general_purpose/system_calls.py +++ b/src/arch/x86/isa/insts/general_purpose/system_calls.py @@ -57,14 +57,14 @@ microcode = ''' def macroop SYSCALL_64 { # All 1s. - limm t1, "(uint64_t)(-1)" + limm t1, "(uint64_t)(-1)", dataSize=8 # Save the next RIP. rdip rcx # Stick rflags with RF masked into r11. rflags t2 - limm t3, "~RFBit" + limm t3, "~RFBit", dataSize=8 andi r11, t2, t3, dataSize=8 rdval t3, star @@ -78,7 +78,7 @@ def macroop SYSCALL_64 # Not writable, read/execute-able, not expandDown, # dpl=0, defaultSize=0, long mode limm t4, ((0 << 0) | (1 << 1) | (0 << 2) | \ - (0 << 3) | (0 << 5) | (1 << 6)) + (0 << 3) | (0 << 5) | (1 << 6)), dataSize=8 wrattr cs, t4 # Set up SS. @@ -89,7 +89,7 @@ def macroop SYSCALL_64 # Writable, readable, not expandDown, # dpl=0, defaultSize=0, not long mode limm t4, ((1 << 0) | (1 << 1) | (0 << 2) | \ - (0 << 3) | (0 << 5) | (0 << 6)) + (0 << 3) | (0 << 5) | (0 << 6)), dataSize=8 wrattr ss, t4 # Set the new rip. @@ -106,14 +106,14 @@ def macroop SYSCALL_64 def macroop SYSCALL_COMPAT { # All 1s. - limm t1, "(uint64_t)(-1)" + limm t1, "(uint64_t)(-1)", dataSize=8 # Save the next RIP. rdip rcx # Stick rflags with RF masked into r11. rflags t2 - limm t3, "~RFBit" + limm t3, "~RFBit", dataSize=8 andi r11, t2, t3, dataSize=8 rdval t3, star @@ -127,7 +127,7 @@ def macroop SYSCALL_COMPAT # Not writable, read/execute-able, not expandDown, # dpl=0, defaultSize=0, long mode limm t4, ((0 << 0) | (1 << 1) | (0 << 2) | \ - (0 << 3) | (0 << 5) | (1 << 6)) + (0 << 3) | (0 << 5) | (1 << 6)), dataSize=8 wrattr cs, t4 # Set up SS. @@ -138,7 +138,7 @@ def macroop SYSCALL_COMPAT # Writable, readable, not expandDown, # dpl=0, defaultSize=0, not long mode limm t4, ((1 << 0) | (1 << 1) | (0 << 2) | \ - (0 << 3) | (0 << 5) | (0 << 6)) + (0 << 3) | (0 << 5) | (0 << 6)), dataSize=8 wrattr ss, t4 # Set the new rip. @@ -160,14 +160,14 @@ def macroop SYSCALL_LEGACY def macroop SYSRET_TO_64 { # All 1s. - limm t1, "(uint64_t)(-1)" + limm t1, "(uint64_t)(-1)", dataSize=8 rdval t3, star srli t3, t3, 48, dataSize=8 ori t3, t3, 3, dataSize=1 # Set rflags to r11 with RF and VM cleared. - limm t4, "~(RFBit | VMBit)" + limm t4, "~(RFBit | VMBit)", dataSize=8 and t4, t4, r11, dataSize=8 wrflags t4, t0 @@ -179,7 +179,7 @@ def macroop SYSRET_TO_64 # Not writable, read/execute-able, not expandDown, # dpl=3, defaultSize=0, long mode limm t4, ((0 << 0) | (1 << 1) | (0 << 2) | \ - (3 << 3) | (0 << 5) | (1 << 6)) + (3 << 3) | (0 << 5) | (1 << 6)), dataSize=8 wrattr cs, t4 # Only the selector is changed for SS. @@ -193,14 +193,14 @@ def macroop SYSRET_TO_64 def macroop SYSRET_TO_COMPAT { # All 1s. - limm t1, "(uint64_t)(-1)" + limm t1, "(uint64_t)(-1)", dataSize=8 rdval t3, star srli t3, t3, 48, dataSize=8 ori t3, t3, 3, dataSize=1 # Set rflags to r11 with RF and VM cleared. - limm t4, "~(RFBit | VMBit)" + limm t4, "~(RFBit | VMBit)", dataSize=8 and t4, t4, r11, dataSize=8 wrflags t4, t0 @@ -211,7 +211,7 @@ def macroop SYSRET_TO_COMPAT # Not writable, read/execute-able, not expandDown, # dpl=3, defaultSize=1, not long mode limm t4, ((0 << 0) | (1 << 1) | (0 << 2) | \ - (3 << 3) | (1 << 5) | (0 << 6)) + (3 << 3) | (1 << 5) | (0 << 6)), dataSize=8 wrattr cs, t4 # Only the selector is changed for SS. diff --git a/src/arch/x86/isa/insts/romutil.py b/src/arch/x86/isa/insts/romutil.py index aa013dbd1..2fcc56e8a 100644 --- a/src/arch/x86/isa/insts/romutil.py +++ b/src/arch/x86/isa/insts/romutil.py @@ -164,8 +164,8 @@ def rom # The type field of the original gate starts at bit 40. # Set the TF, NT, and RF bits. We'll flip them at the end. - limm t6, (1 << 8) | (1 << 14) | (1 << 16) - or t10, t10, t6 + limm t6, (1 << 8) | (1 << 14) | (1 << 16), dataSize=8 + or t10, t10, t6, dataSize=8 srli t5, t4, 40, dataSize=8 srli t7, t10, 9, dataSize=8 xor t5, t7, t5, dataSize=8 diff --git a/src/arch/x86/isa/insts/system/segmentation.py b/src/arch/x86/isa/insts/system/segmentation.py index acbca9f6e..b83fcba95 100644 --- a/src/arch/x86/isa/insts/system/segmentation.py +++ b/src/arch/x86/isa/insts/system/segmentation.py @@ -171,7 +171,7 @@ def macroop LIDT_16_P def macroop LTR_R { chks reg, t0, TRCheck - limm t4, 0 + limm t4, 0, dataSize=8 srli t4, reg, 3, dataSize=2 ldst t1, tsg, [8, t4, t0], dataSize=8 ld t2, tsg, [8, t4, t0], 8, dataSize=8 @@ -187,7 +187,7 @@ def macroop LTR_M { ld t5, seg, sib, disp, dataSize=2 chks t5, t0, TRCheck - limm t4, 0 + limm t4, 0, dataSize=8 srli t4, t5, 3, dataSize=2 ldst t1, tsg, [8, t4, t0], dataSize=8 ld t2, tsg, [8, t4, t0], 8, dataSize=8 @@ -204,7 +204,7 @@ def macroop LTR_P rdip t7 ld t5, seg, riprel, disp, dataSize=2 chks t5, t0, TRCheck - limm t4, 0 + limm t4, 0, dataSize=8 srli t4, t5, 3, dataSize=2 ldst t1, tsg, [8, t4, t0], dataSize=8 ld t2, tsg, [8, t4, t0], 8, dataSize=8 @@ -220,7 +220,7 @@ def macroop LLDT_R { chks reg, t0, InGDTCheck, flags=(EZF,) br label("end"), flags=(CEZF,) - limm t4, 0 + limm t4, 0, dataSize=8 srli t4, reg, 3, dataSize=2 ldst t1, tsg, [8, t4, t0], dataSize=8 ld t2, tsg, [8, t4, t0], 8, dataSize=8 @@ -237,7 +237,7 @@ def macroop LLDT_M ld t5, seg, sib, disp, dataSize=2 chks t5, t0, InGDTCheck, flags=(EZF,) br label("end"), flags=(CEZF,) - limm t4, 0 + limm t4, 0, dataSize=8 srli t4, t5, 3, dataSize=2 ldst t1, tsg, [8, t4, t0], dataSize=8 ld t2, tsg, [8, t4, t0], 8, dataSize=8 @@ -255,7 +255,7 @@ def macroop LLDT_P ld t5, seg, riprel, disp, dataSize=2 chks t5, t0, InGDTCheck, flags=(EZF,) br label("end"), flags=(CEZF,) - limm t4, 0 + limm t4, 0, dataSize=8 srli t4, t5, 3, dataSize=2 ldst t1, tsg, [8, t4, t0], dataSize=8 ld t2, tsg, [8, t4, t0], 8, dataSize=8 -- 2.30.2