From 3f0d346956192e53af991cf6bbe65ee18f1ed32f Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Tue, 7 Jun 2022 16:55:21 +0100
Subject: [PATCH]

---
 openpower/sv/compliancy_levels.mdwn | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/openpower/sv/compliancy_levels.mdwn b/openpower/sv/compliancy_levels.mdwn
index abba7bf4a..c9b820622 100644
--- a/openpower/sv/compliancy_levels.mdwn
+++ b/openpower/sv/compliancy_levels.mdwn
@@ -16,3 +16,11 @@ To achieve full soft-emulated interoperability, all implementations
 **must**, at the bare minimum, raise Illegal Instruction traps for
 all SPRs including all reserved SPRs, all SVP64-related Context
 instructions (REMAP), as well as for the entire SVP64 Prefix space.
+
+Summary of Compliancy Levels, each Level includes all lower levels:
+
+* **Ultra-embedded**: `setvl` instruction and context-switching of SVSTATE
+  into SVSRR1. Register Files as Standard Power ISA.
+* **Embedded**: `svstep` instruction, all SV Branch instructions,
+  and support for Hardware for-looping
+  in both Horizontal-First and Vertical-First Mode as well as Predication
-- 
2.30.2