From 3f22f48eeb98eb3407f735a3fd254c49043902e9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 4 Oct 2017 18:30:42 +0200 Subject: [PATCH] Add blackbox command --- passes/cmds/Makefile.inc | 1 + passes/cmds/blackbox.cc | 81 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+) create mode 100644 passes/cmds/blackbox.cc diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index 1dbb439ca..9e3934e16 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -27,4 +27,5 @@ OBJS += passes/cmds/qwp.o OBJS += passes/cmds/edgetypes.o OBJS += passes/cmds/chformal.o OBJS += passes/cmds/chtype.o +OBJS += passes/cmds/blackbox.o diff --git a/passes/cmds/blackbox.cc b/passes/cmds/blackbox.cc new file mode 100644 index 000000000..497b35f5c --- /dev/null +++ b/passes/cmds/blackbox.cc @@ -0,0 +1,81 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct BlackboxPass : public Pass { + BlackboxPass() : Pass("blackbox", "change type of cells in the design") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" blackbox [options] [selection]\n"); + log("\n"); + log("Convert modules into blackbox modules (remove contents and set the blackbox\n"); + log("module attribute).\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) + { + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + // if (args[argidx] == "-???") { + // continue; + // } + break; + } + extra_args(args, argidx, design); + + for (auto module : design->selected_whole_modules_warn()) + { + pool remove_cells; + pool remove_wires; + + for (auto cell : module->cells()) + remove_cells.insert(cell); + + for (auto wire : module->wires()) + if (wire->port_id == 0) + remove_wires.insert(wire); + + for (auto it = module->memories.begin(); it != module->memories.end(); ++it) + delete it->second; + module->memories.clear(); + + for (auto it = module->processes.begin(); it != module->processes.end(); ++it) + delete it->second; + module->processes.clear(); + + module->new_connections(std::vector()); + + for (auto cell : remove_cells) + module->remove(cell); + + module->remove(remove_wires); + + module->set_bool_attribute("\\blackbox"); + } + } +} BlackboxPass; + +PRIVATE_NAMESPACE_END -- 2.30.2