From 3f267d5d1449fb66fe88192d50aa03aa0e21d1aa Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 22 Apr 2021 15:15:07 +0000 Subject: [PATCH] make placement of SRAMs optional, and PLL as well, in experiment9 freepdk45 --- experiments9/doDesign.py | 4 +- experiments9/freepdk_c4m45/doDesign.py | 80 +++++++++++++++----------- 2 files changed, 47 insertions(+), 37 deletions(-) diff --git a/experiments9/doDesign.py b/experiments9/doDesign.py index 916e20c..86b1d12 100644 --- a/experiments9/doDesign.py +++ b/experiments9/doDesign.py @@ -25,7 +25,7 @@ def scriptMain (**kw): """The mandatory function to be called by Coriolis CGT/Unicorn.""" global af rvalue = True - coreSize = 70000 + coreSize = 65000 cwd = os.path.split( os.path.abspath(__file__) )[0] ioSpecs = IoSpecs() ioSpecs.loadFromPinmux( '{}/ls180/litex_pinpads.json'.format(cwd) ) @@ -45,7 +45,7 @@ def scriptMain (**kw): ls180Conf.cfg.etesian.spaceMargin = 0.05 #ls180Conf.cfg.katana.hTracksReservedLocal = 6 #ls180Conf.cfg.katana.vTracksReservedLocal = 3 - ls180Conf.cfg.katana.hTracksReservedMin = 9 + ls180Conf.cfg.katana.hTracksReservedMin = 6 ls180Conf.cfg.katana.vTracksReservedMin = 1 ls180Conf.cfg.block.spareSide = l(700) ls180Conf.cfg.chip.padCoreSide = 'North' diff --git a/experiments9/freepdk_c4m45/doDesign.py b/experiments9/freepdk_c4m45/doDesign.py index 37d2ebb..a134277 100644 --- a/experiments9/freepdk_c4m45/doDesign.py +++ b/experiments9/freepdk_c4m45/doDesign.py @@ -254,43 +254,53 @@ def scriptMain (**kw): chipBuilder.doChipFloorplan() with UpdateSession(): + ####### + # placement of SRAM blackboxes, manually + # Thoses ids are dependent on Yosys. They need to be adjusted # whenever the design changes. - #tiId = 38695 - # tiId = 38381 - #sramId = 3695 - # sramId = 3300 - # tiPath = 'subckt_{}_test_issuer.subckt_1_ti.'.format(tiId) - # sramPaths = [ tiPath+'subckt_{}_sram4k_0.subckt_144_SPBlock_512W64B8W'.format(sramId) - # , tiPath+'subckt_{}_sram4k_1.subckt_144_SPBlock_512W64B8W'.format(sramId+1) - # , tiPath+'subckt_{}_sram4k_2.subckt_144_SPBlock_512W64B8W'.format(sramId+2) - # , tiPath+'subckt_{}_sram4k_3.subckt_144_SPBlock_512W64B8W'.format(sramId+3) - # ] - # sram = DataBase.getDB().getCell( 'SPBlock_512W64B8W' ) - # if sram: - # sramAb = sram.getAbutmentBox() - # coreAb = cell.getAbutmentBox() - # sliceHeight = chipBuilder.conf.sliceHeight - # originX = coreAb.getXMin() + 2*chipBuilder.conf.sliceStep - # for i in range(4): - # sram = rgetInstance( cell, sramPaths[i] ) - # y = coreAb.getYMax() - sramAb.getHeight() - 2*sliceHeight - # chipBuilder.placeMacro \ - # ( sramPaths[i] - # , Transformation( originX - # , y - # , Transformation.Orientation.ID ) - # ) - # originX += sramAb.getWidth () + 3*sliceHeight - # else: - # print (ErrorMessage( 1, 'SRAM instance not found.')) - pll = addPllPlaceHolder( cell ) - pllAb = pll.getAbutmentBox() - t = Transformation( coreAb.getXMax() - pllAb.getWidth() - , coreAb.getYMax() - pllAb.getHeight() - , Transformation.Orientation.ID ) - pll.setTransformation( t ) - pll.setPlacementStatus( Instance.PlacementStatus.FIXED ) + tiId = 38695 + tiId = 38381 + sramId = 3695 + sramId = 3300 + tiPath = 'subckt_{}_test_issuer.subckt_1_ti.'.format(tiId) + sramPaths = [ tiPath+'subckt_{}_sram4k_0.subckt_144_SPBlock_512W64B8W'.format(sramId) + , tiPath+'subckt_{}_sram4k_1.subckt_144_SPBlock_512W64B8W'.format(sramId+1) + , tiPath+'subckt_{}_sram4k_2.subckt_144_SPBlock_512W64B8W'.format(sramId+2) + , tiPath+'subckt_{}_sram4k_3.subckt_144_SPBlock_512W64B8W'.format(sramId+3) + ] + # each sram is named differently (yosys blackbox issue) + for i in range(4): + sram = DataBase.getDB().getCell( 'spblock512w64b8w_%i' ) + if sram: + sramAb = sram.getAbutmentBox() + coreAb = cell.getAbutmentBox() + sliceHeight = chipBuilder.conf.sliceHeight + originX = coreAb.getXMin() + 2*chipBuilder.conf.sliceStep + sram = rgetInstance( cell, sramPaths[i] ) + y = coreAb.getYMax() - sramAb.getHeight() - 2*sliceHeight + t = Transformation( originX + , y + , Transformation.Orientation.ID ) + chipBuilder.placeMacro ( sramPaths[i], t ) + originX += sramAb.getWidth () + 3*sliceHeight + else: + print (ErrorMessage( 1, 'SRAM instance %d not found.' % i)) + + ######### + # manual placement of PLL + pll = DataBase.getDB().getCell( 'pll' ) + # skip PLL cell for now: Alliance cannot cope with no ports + if pll is None and False: + pll = addPllPlaceHolder( cell ) + if pll: + pllAb = pll.getAbutmentBox() + t = Transformation( coreAb.getXMax() - pllAb.getWidth() + , coreAb.getYMax() - pllAb.getHeight() + , Transformation.Orientation.ID ) + pll.setTransformation( t ) + pll.setPlacementStatus( Instance.PlacementStatus.FIXED ) + #ls180Conf.placeArea = Box( coreAb.getXMin() # , coreAb.getYMin() # , coreAb.getXMax() - -- 2.30.2