From 3f43a493820a30459671b023df3d2ce0e79b303e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 10 Nov 2015 16:43:38 +0100 Subject: [PATCH] soc: merge with misoc 3fcc4f116c3292020cb811d179e45ae45990101b changes: -software/bios: remove dataflow -cores/identifier: replace with user-defined string -interconnect/CSRBankArray: support read-only mappings -targets: Added Numato Mimas V2 target -Our libunwind changes were merged upstream. -wishbone: update TODO -replace Counter in Converters -Fix CSRBankArray -flterm: properly exit on ^C. --- litex/soc/cores/identifier.py | 24 +++++++-------- litex/soc/integration/soc_core.py | 24 +++++++-------- litex/soc/integration/soc_sdram.py | 2 +- litex/soc/interconnect/csr_bus.py | 7 ++++- litex/soc/interconnect/wishbone.py | 46 ++++++++++++++++++---------- litex/soc/software/bios/boot.c | 2 +- litex/soc/software/bios/main.c | 32 ++++++------------- litex/soc/software/include/base/id.h | 4 +-- litex/soc/software/libbase/id.c | 22 ++++++------- litex/soc/software/libbase/time.c | 2 +- litex/soc/software/libnet/microudp.c | 2 +- litex/soc/tools/flterm.py | 1 - 12 files changed, 85 insertions(+), 83 deletions(-) diff --git a/litex/soc/cores/identifier.py b/litex/soc/cores/identifier.py index 2ed151f8..5baedca1 100644 --- a/litex/soc/cores/identifier.py +++ b/litex/soc/cores/identifier.py @@ -1,16 +1,14 @@ from litex.gen import * -from litex.soc.interconnect.csr import * - -class Identifier(Module, AutoCSR): - def __init__(self, sysid, frequency, revision=None): - self._sysid = CSRStatus(16) - self._frequency = CSRStatus(32) - - ### - - self.comb += [ - self._sysid.status.eq(sysid), - self._frequency.status.eq(frequency) - ] +class Identifier(Module): + def __init__(self, ident): + contents = list(ident.encode()) + l = len(contents) + if l > 255: + raise ValueError("Identifier string must be 255 characters or less") + contents.insert(0, l) + self.mem = Memory(8, len(contents), init=contents) + + def get_memories(self): + return [(True, self.mem)] diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 315af070..4f55e9c0 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -16,13 +16,13 @@ def mem_decoder(address, start=26, end=29): class SoCCore(Module): csr_map = { - "crg": 0, # user - "uart_phy": 1, # provided by default (optional) - "uart": 2, # provided by default (optional) - "identifier": 3, # provided by default (optional) - "timer0": 4, # provided by default (optional) - "buttons": 5, # user - "leds": 6, # user + "crg": 0, # user + "uart_phy": 1, # provided by default (optional) + "uart": 2, # provided by default (optional) + "identifier_mem": 3, # provided by default (optional) + "timer0": 4, # provided by default (optional) + "buttons": 5, # user + "leds": 6, # user } interrupt_map = { "uart": 0, @@ -42,7 +42,7 @@ class SoCCore(Module): shadow_base=0x80000000, csr_data_width=8, csr_address_width=14, with_uart=True, uart_baudrate=115200, - with_identifier=True, + ident="", with_timer=True): self.platform = platform self.clk_freq = clk_freq @@ -59,8 +59,6 @@ class SoCCore(Module): self.with_uart = with_uart self.uart_baudrate = uart_baudrate - self.with_identifier = with_identifier - self.shadow_base = shadow_base self.csr_data_width = csr_data_width @@ -103,9 +101,9 @@ class SoCCore(Module): self.submodules.uart_phy = uart.RS232PHY(platform.request("serial"), clk_freq, uart_baudrate) self.submodules.uart = uart.UART(self.uart_phy) - if with_identifier: - platform_id = 0x554E if not hasattr(platform, "identifier") else platform.identifier - self.submodules.identifier = identifier.Identifier(platform_id, int(clk_freq)) + if ident: + self.submodules.identifier = identifier.Identifier(ident) + self.add_constant("SYSTEM_CLOCK_FREQUENCY", int(clk_freq)) if with_timer: self.submodules.timer0 = timer.Timer() diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py index 8ad63009..3c3a3e83 100644 --- a/litex/soc/integration/soc_sdram.py +++ b/litex/soc/integration/soc_sdram.py @@ -43,7 +43,7 @@ class SoCSDRAM(SoCCore): def __init__(self, platform, clk_freq, l2_size=8192, **kwargs): SoCCore.__init__(self, platform, clk_freq, **kwargs) self.l2_size = l2_size - + self._sdram_phy = [] self._wb_sdram_ifs = [] self._wb_sdram = wishbone.Interface() diff --git a/litex/soc/interconnect/csr_bus.py b/litex/soc/interconnect/csr_bus.py index b27c256f..12819927 100644 --- a/litex/soc/interconnect/csr_bus.py +++ b/litex/soc/interconnect/csr_bus.py @@ -152,11 +152,16 @@ class CSRBankArray(Module): if hasattr(obj, "get_memories"): memories = obj.get_memories() for memory in memories: + if isinstance(memory, tuple): + read_only, memory = memory + else: + read_only = False mapaddr = self.address_map(name, memory) if mapaddr is None: continue sram_bus = Interface(*ifargs, **ifkwargs) - mmap = csr.SRAM(memory, mapaddr, bus=sram_bus) + mmap = SRAM(memory, mapaddr, read_only=read_only, + bus=sram_bus) self.submodules += mmap csrs += mmap.get_csrs() self.srams.append((name, memory, mapaddr, mmap)) diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py index a2070fa4..c10cda4e 100644 --- a/litex/soc/interconnect/wishbone.py +++ b/litex/soc/interconnect/wishbone.py @@ -175,15 +175,22 @@ class DownConverter(Module): read = Signal() write = Signal() - counter = Counter(max=ratio) - self.submodules += counter + counter = Signal(max=ratio) + counter_reset = Signal() + counter_ce = Signal() + self.sync += \ + If(counter_reset, + counter.eq(0) + ).Elif(counter_ce, + counter.eq(counter + 1) + ) counter_done = Signal() - self.comb += counter_done.eq(counter.value == ratio-1) + self.comb += counter_done.eq(counter == ratio-1) # Main FSM self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", - counter.reset.eq(1), + counter_reset.eq(1), If(master.stb & master.cyc, If(master.we, NextState("WRITE") @@ -199,7 +206,7 @@ class DownConverter(Module): If(master.stb & master.cyc, slave.stb.eq(1), If(slave.ack, - counter.ce.eq(1), + counter_ce.eq(1), If(counter_done, master.ack.eq(1), NextState("IDLE") @@ -215,7 +222,7 @@ class DownConverter(Module): If(master.stb & master.cyc, slave.stb.eq(1), If(slave.ack, - counter.ce.eq(1), + counter_ce.eq(1), If(counter_done, master.ack.eq(1), NextState("IDLE") @@ -233,7 +240,7 @@ class DownConverter(Module): ).Else( slave.cti.eq(2) ), - slave.adr.eq(Cat(counter.value, master.adr)) + slave.adr.eq(Cat(counter, master.adr)) ] # Datapath @@ -243,13 +250,13 @@ class DownConverter(Module): slave.sel.eq(master.sel[i*dw_to//8:(i+1)*dw_to]), slave.dat_w.eq(master.dat_w[i*dw_to:(i+1)*dw_to]) ] - self.comb += Case(counter.value, cases) + self.comb += Case(counter, cases) cached_data = Signal(dw_from) self.comb += master.dat_r.eq(Cat(cached_data[dw_to:], slave.dat_r)) self.sync += \ - If(read & counter.ce, + If(read & counter_ce, cached_data.eq(master.dat_r) ) @@ -287,13 +294,20 @@ class UpConverter(Module): self.submodules += address self.comb += address.d.eq(master.adr) - counter = Counter(max=ratio) - self.submodules += counter + counter = Signal(max=ratio) + counter_ce = Signal() + counter_reset = Signal() + self.sync += \ + If(counter_reset, + counter.eq(0) + ).Elif(counter_ce, + counter.eq(counter + 1) + ) counter_offset = Signal(max=ratio) counter_done = Signal() self.comb += [ counter_offset.eq(address.q), - counter_done.eq((counter.value + counter_offset) == ratio-1) + counter_done.eq((counter + counter_offset) == ratio-1) ] cached_data = Signal(dw_to) @@ -314,7 +328,7 @@ class UpConverter(Module): # Main FSM self.submodules.fsm = fsm = FSM() fsm.act("IDLE", - counter.reset.eq(1), + counter_reset.eq(1), If(master.stb & master.cyc, address.ce.eq(1), If(master.we, @@ -331,7 +345,7 @@ class UpConverter(Module): fsm.act("WRITE", If(master.stb & master.cyc, write.eq(1), - counter.ce.eq(1), + counter_ce.eq(1), master.ack.eq(1), If(counter_done, NextState("EVICT") @@ -384,7 +398,7 @@ class UpConverter(Module): write_sel = Signal() cases[i] = write_sel.eq(1) self.comb += [ - cached_sels[i].reset.eq(counter.reset), + cached_sels[i].reset.eq(counter_reset), If(write, cached_datas[i].d.eq(master.dat_w), ).Else( @@ -396,7 +410,7 @@ class UpConverter(Module): cached_sels[i].ce.eq(1) ) ] - self.comb += Case(counter.value + counter_offset, cases) + self.comb += Case(counter + counter_offset, cases) cases = {} for i in range(ratio): diff --git a/litex/soc/software/bios/boot.c b/litex/soc/software/bios/boot.c index 0430aca7..635bd649 100644 --- a/litex/soc/software/bios/boot.c +++ b/litex/soc/software/bios/boot.c @@ -34,7 +34,7 @@ static int check_ack(void) timer0_en_write(0); timer0_reload_write(0); - timer0_load_write(identifier_frequency_read()/4); + timer0_load_write(SYSTEM_CLOCK_FREQUENCY/4); timer0_en_write(1); timer0_update_value_write(1); recognized = 0; diff --git a/litex/soc/software/bios/main.c b/litex/soc/software/bios/main.c index 0deb9e90..bda64db4 100644 --- a/litex/soc/software/bios/main.c +++ b/litex/soc/software/bios/main.c @@ -13,7 +13,6 @@ #include #include "sdram.h" -#include "dataflow.h" #include "boot.h" /* General address space functions */ @@ -176,6 +175,14 @@ static void crc(char *startaddr, char *len) printf("CRC32: %08x\n", crc32((unsigned char *)addr, length)); } +static void ident(void) +{ + char buffer[IDENT_SIZE]; + + get_ident(buffer); + printf("Ident: %s\n", buffer); +} + #ifdef __lm32__ enum { CSR_IE = 1, CSR_IM, CSR_IP, CSR_ICC, CSR_DCC, CSR_CC, CSR_CFG, CSR_EBA, @@ -288,23 +295,6 @@ static void wcsr(char *csr, char *value) #endif /* __lm32__ */ -static void dfs(char *baseaddr) -{ - char *c; - unsigned int addr; - - if(*baseaddr == 0) { - printf("dfs
\n"); - return; - } - addr = strtoul(baseaddr, &c, 0); - if(*c != 0) { - printf("incorrect address\n"); - return; - } - print_isd_info(addr); -} - /* Init + command line */ static void help(void) @@ -361,6 +351,7 @@ static void do_command(char *c) else if(strcmp(token, "mw") == 0) mw(get_token(&c), get_token(&c), get_token(&c)); else if(strcmp(token, "mc") == 0) mc(get_token(&c), get_token(&c), get_token(&c)); else if(strcmp(token, "crc") == 0) crc(get_token(&c), get_token(&c)); + else if(strcmp(token, "ident") == 0) ident(); #ifdef L2_SIZE else if(strcmp(token, "flushl2") == 0) flush_l2_cache(); @@ -401,8 +392,6 @@ static void do_command(char *c) else if(strcmp(token, "sdrinit") == 0) sdrinit(); #endif - else if(strcmp(token, "dfs") == 0) dfs(get_token(&c)); - else if(strcmp(token, "") != 0) printf("Command not found\n"); } @@ -479,7 +468,7 @@ static int test_user_abort(void) #endif timer0_en_write(0); timer0_reload_write(0); - timer0_load_write(identifier_frequency_read()*2); + timer0_load_write(SYSTEM_CLOCK_FREQUENCY*2); timer0_en_write(1); timer0_update_value_write(1); while(timer0_value_read()) { @@ -538,7 +527,6 @@ int main(int i, char **c) "(c) Copyright 2007-2015 M-Labs Limited\n" "Built "__DATE__" "__TIME__"\n"); crcbios(); - id_print(); #ifdef CSR_ETHMAC_BASE eth_init(); #endif diff --git a/litex/soc/software/include/base/id.h b/litex/soc/software/include/base/id.h index 89b540f6..bccbd558 100644 --- a/litex/soc/software/include/base/id.h +++ b/litex/soc/software/include/base/id.h @@ -5,8 +5,8 @@ extern "C" { #endif -void get_sysid_formatted(char *sysid); -void id_print(void); +#define IDENT_SIZE 256 +void get_ident(char *ident); #ifdef __cplusplus } diff --git a/litex/soc/software/libbase/id.c b/litex/soc/software/libbase/id.c index 863912ab..093b9939 100644 --- a/litex/soc/software/libbase/id.c +++ b/litex/soc/software/libbase/id.c @@ -4,17 +4,17 @@ #include #include -void get_sysid_formatted(char *sysid) -{ - sysid[0] = identifier_sysid_read() >> 8; - sysid[1] = identifier_sysid_read(); - sysid[2] = 0; -} -void id_print(void) +void get_ident(char *ident) { - char sysid[3]; - - get_sysid_formatted(sysid); - printf("Running on LiteX SoC (sysid:%s) at %dMHz\n", sysid, identifier_frequency_read()/1000000); +#ifdef CSR_IDENTIFIER_MEM_BASE + int len, i; + + len = MMPTR(CSR_IDENTIFIER_MEM_BASE); + for(i=0;i