From 3f4460a1869ccfd6225379d18ade195f165841a4 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 1 Jan 2020 07:20:06 +0000 Subject: [PATCH] ice40: match memory inference attribute values case insensitive. LSE/Synplify use case insensitive matching. --- techlibs/ice40/brams.txt | 1 + tests/arch/ice40/memories.ys | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/techlibs/ice40/brams.txt b/techlibs/ice40/brams.txt index d51c7119a..36dfddab2 100644 --- a/techlibs/ice40/brams.txt +++ b/techlibs/ice40/brams.txt @@ -30,6 +30,7 @@ endbram # The syn_* attributes are described in: # https://www.latticesemi.com/-/media/LatticeSemi/Documents/Tutorials/AK/LatticeDiamondTutorial311.ashx +attr_icase 1 match $__ICE40_RAM4K_M0 # implicitly requested RAM or ROM diff --git a/tests/arch/ice40/memories.ys b/tests/arch/ice40/memories.ys index 83386f0ec..43bcf2452 100644 --- a/tests/arch/ice40/memories.ys +++ b/tests/arch/ice40/memories.ys @@ -34,6 +34,12 @@ setattr -set syn_ramstyle "block_ram" m:memory synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:SB_RAM40_4K +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +setattr -set syn_ramstyle "Block_RAM" m:memory +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:SB_RAM40_4K # any case works + design -reset; read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp setattr -set ram_block 1 m:memory -- 2.30.2