From 3f6b640e93d67b7dde2d845a61a2300ad8bc86a5 Mon Sep 17 00:00:00 2001 From: whitequark Date: Tue, 24 Sep 2019 14:14:45 +0000 Subject: [PATCH] build.plat,lib.cdc,vendor: unify platform related diagnostics. NFC. --- nmigen/build/plat.py | 20 ++++++++++---------- nmigen/lib/cdc.py | 10 ++++++---- nmigen/vendor/xilinx_spartan_3_6.py | 10 ++++++---- 3 files changed, 22 insertions(+), 18 deletions(-) diff --git a/nmigen/build/plat.py b/nmigen/build/plat.py index d5c1060..30800ec 100644 --- a/nmigen/build/plat.py +++ b/nmigen/build/plat.py @@ -37,7 +37,7 @@ class Platform(ResourceManager, metaclass=ABCMeta): def default_clk_constraint(self): if self.default_clk is None: raise AttributeError("Platform '{}' does not define a default clock" - .format(self.__class__.__name__)) + .format(type(self).__name__)) return self.lookup(self.default_clk).clock @property @@ -45,7 +45,7 @@ class Platform(ResourceManager, metaclass=ABCMeta): constraint = self.default_clk_constraint if constraint is None: raise AttributeError("Platform '{}' does not constrain its default clock" - .format(self.__class__.__name__)) + .format(type(self).__name__)) return constraint.frequency def add_file(self, filename, content): @@ -154,20 +154,20 @@ class Platform(ResourceManager, metaclass=ABCMeta): """ Extract bitstream for fragment ``name`` from ``products`` and download it to a target. """ - raise NotImplementedError("Platform {} does not support programming" - .format(self.__class__.__name__)) + raise NotImplementedError("Platform '{}' does not support programming" + .format(type(self).__name__)) def _check_feature(self, feature, pin, attrs, valid_xdrs, valid_attrs): if not valid_xdrs: - raise NotImplementedError("Platform {} does not support {}" - .format(self.__class__.__name__, feature)) + raise NotImplementedError("Platform '{}' does not support {}" + .format(type(self).__name__, feature)) elif pin.xdr not in valid_xdrs: - raise NotImplementedError("Platform {} does not support {} for XDR {}" - .format(self.__class__.__name__, feature, pin.xdr)) + raise NotImplementedError("Platform '{}' does not support {} for XDR {}" + .format(type(self).__name__, feature, pin.xdr)) if not valid_attrs and attrs: - raise NotImplementedError("Platform {} does not support attributes for {}" - .format(self.__class__.__name__, feature)) + raise NotImplementedError("Platform '{}' does not support attributes for {}" + .format(type(self).__name__, feature)) @staticmethod def _invert_if(invert, value): diff --git a/nmigen/lib/cdc.py b/nmigen/lib/cdc.py index 9e0ad72..2bf1beb 100644 --- a/nmigen/lib/cdc.py +++ b/nmigen/lib/cdc.py @@ -83,8 +83,9 @@ class FFSynchronizer(Elaboratable): return platform.get_ff_sync(self) if self._max_input_delay is not None: - raise NotImplementedError("Platform {!r} does not support constraining input delay " - "for FFSynchronizer".format(platform)) + raise NotImplementedError("Platform '{}' does not support constraining input delay " + "for FFSynchronizer" + .format(type(platform).__name__)) m = Module() flops = [Signal(self.i.shape(), name="stage{}".format(index), @@ -145,8 +146,9 @@ class ResetSynchronizer(Elaboratable): return platform.get_reset_sync(self) if self._max_input_delay is not None: - raise NotImplementedError("Platform {!r} does not support constraining input delay " - "for ResetSynchronizer".format(platform)) + raise NotImplementedError("Platform '{}' does not support constraining input delay " + "for ResetSynchronizer" + .format(type(platform).__name__)) m = Module() m.domains += ClockDomain("reset_sync", async_reset=True, local=True) diff --git a/nmigen/vendor/xilinx_spartan_3_6.py b/nmigen/vendor/xilinx_spartan_3_6.py index aafb3f8..57ba13a 100644 --- a/nmigen/vendor/xilinx_spartan_3_6.py +++ b/nmigen/vendor/xilinx_spartan_3_6.py @@ -418,8 +418,9 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform): def get_ff_sync(self, ff_sync): if ff_sync._max_input_delay is not None: - raise NotImplementedError("Platform {!r} does not support constraining input delay " - "for FFSynchronizer".format(self)) + raise NotImplementedError("Platform '{}' does not support constraining input delay " + "for FFSynchronizer" + .format(type(self).__name__)) m = Module() flops = [Signal(ff_sync.i.shape(), name="stage{}".format(index), @@ -433,8 +434,9 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform): def get_reset_sync(self, reset_sync): if reset_sync._max_input_delay is not None: - raise NotImplementedError("Platform {!r} does not support constraining input delay " - "for ResetSynchronizer".format(self)) + raise NotImplementedError("Platform '{}' does not support constraining input delay " + "for ResetSynchronizer" + .format(type(self).__name__)) m = Module() m.domains += ClockDomain("reset_sync", async_reset=True, local=True) -- 2.30.2