From 3f78e32b5be7a1db9efe080efa97be12a1b8d831 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Wed, 21 Apr 2021 20:48:38 +0200 Subject: [PATCH] testcase: pass PRTBL to mmu --- src/soc/simple/test/test_core.py | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index a7387e85..f25d250c 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -35,6 +35,16 @@ from soc.fu.branch.test.test_pipe_caller import BranchTestCase from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase from soc.regfile.util import spr_to_fast_reg +mmu_sprs = ["PRTBL"] + +def set_mmu_spr(name, i, val, core): #important keep pep8 formatting + fsm = core.fus.fus["mmu0"].alu + yield fsm.mmu.l_in.mtspr.eq(1) + yield fsm.mmu.l_in.sprn.eq(i) + yield fsm.mmu.l_in.rs.eq(val) + yield + yield fsm.mmu.l_in.mtspr.eq(0) + print("mmu_spr was updated") def setup_regs(pdecode2, core, test): @@ -104,7 +114,10 @@ def setup_regs(pdecode2, core, test): if sprname == x.name: print("setting slow SPR %d (%s) to %x" % (i, sprname, val)) - yield sregs.memory._array[i].eq(val) + if not sprname in mmu_sprs: + yield sregs.memory._array[i].eq(val) + else: + yield from set_mmu_spr(sprname, i, val, core) else: yield fregs.regs[fast].reg.eq(val) print("setting fast reg %d (%s) to %x" % -- 2.30.2