From 3fa88540f59d9cb8faa2c71abc09d9f487a0b949 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 9 Mar 2019 22:35:32 +0000 Subject: [PATCH] rename input variable to i (input is a python keyword) --- TLB/test/test_vector_assembler.py | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/TLB/test/test_vector_assembler.py b/TLB/test/test_vector_assembler.py index 721d8627..9e9192a2 100644 --- a/TLB/test/test_vector_assembler.py +++ b/TLB/test/test_vector_assembler.py @@ -15,14 +15,14 @@ assembler_size = 4 # Arguments: # dut: The CamEntry being tested # input: The array of single bits to be written -def set_assembler(dut, input): - assert len(input) == assembler_size +def set_assembler(dut, i): + assert len(i) == assembler_size for index in range(assembler_size): # Make sure we start from the beginning of the array # at least the side that makes sense from a human standpoint # of reading bits input_index = assembler_size - index - 1 - yield dut.input[index].eq(input[input_index]) + yield dut.i[index].eq(i[input_index]) yield # Checks the output of the VectorAssembler @@ -37,14 +37,14 @@ def check_output(dut, o, op): def testbench(dut): # Input should but bit readable from left to right # with Little Endian notation - input = [1, 1, 0, 0] + i = [1, 1, 0, 0] output = 12 - yield from set_assembler(dut, input) + yield from set_assembler(dut, i) yield from check_output(dut, output, 0) - input = [1, 1, 0, 1] + i = [1, 1, 0, 1] output = 13 - yield from set_assembler(dut, input) + yield from set_assembler(dut, i) yield from check_output(dut, output, 0) if __name__ == "__main__": -- 2.30.2