From 3fc5f170e6a81396adf3e1d72676f55fd0534dee Mon Sep 17 00:00:00 2001 From: whitequark Date: Sat, 15 Jun 2019 16:07:40 +0000 Subject: [PATCH] vendor.xilinx_{7series,spartan6}: emit IBUF/OBUF explicitly. Do this to make sure all buffers, tristate/differential or not, are instantiated the exact same way, and are subject to the same set of toolchain bugs, if any. --- nmigen/vendor/xilinx_7series.py | 12 ++++++++++-- nmigen/vendor/xilinx_spartan6.py | 12 ++++++++++-- 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py index c73c87e..0235896 100644 --- a/nmigen/vendor/xilinx_7series.py +++ b/nmigen/vendor/xilinx_7series.py @@ -234,7 +234,11 @@ class Xilinx7SeriesPlatform(TemplatedPlatform): valid_xdrs=(0, 1, 2), valid_attrs=True) m = Module() i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None) - m.d.comb += i.eq(port) + for bit in range(len(port)): + m.submodules += Instance("IBUF", + i_I=port[bit], + o_O=i[bit] + ) return m def get_output(self, pin, port, attrs, invert): @@ -242,7 +246,11 @@ class Xilinx7SeriesPlatform(TemplatedPlatform): valid_xdrs=(0, 1, 2), valid_attrs=True) m = Module() i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None) - m.d.comb += port.eq(o) + for bit in range(len(port)): + m.submodules += Instance("OBUF", + i_I=o[bit], + o_O=port[bit] + ) return m def get_tristate(self, pin, port, attrs, invert): diff --git a/nmigen/vendor/xilinx_spartan6.py b/nmigen/vendor/xilinx_spartan6.py index 7dae410..8158488 100644 --- a/nmigen/vendor/xilinx_spartan6.py +++ b/nmigen/vendor/xilinx_spartan6.py @@ -249,7 +249,11 @@ class XilinxSpartan6Platform(TemplatedPlatform): valid_xdrs=(0, 1, 2), valid_attrs=True) m = Module() i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None) - m.d.comb += i.eq(port) + for bit in range(len(port)): + m.submodules += Instance("IBUF", + i_I=port[bit], + o_O=i[bit] + ) return m def get_output(self, pin, port, attrs, invert): @@ -257,7 +261,11 @@ class XilinxSpartan6Platform(TemplatedPlatform): valid_xdrs=(0, 1, 2), valid_attrs=True) m = Module() i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None) - m.d.comb += port.eq(o) + for bit in range(len(port)): + m.submodules += Instance("OBUF", + i_I=o[bit], + o_O=port[bit] + ) return m def get_tristate(self, pin, port, attrs, invert): -- 2.30.2