From 3fd10728cb1aacf593a7a006ad40e874f791d655 Mon Sep 17 00:00:00 2001 From: Jonathan Wright Date: Fri, 15 Jan 2021 15:48:59 +0000 Subject: [PATCH] aarch64: Use RTL builtins for integer mls_n intrinsics Rewrite integer mls_n Neon intrinsics to use RTL builtins rather than inline assembly code, allowing for better scheduling and optimization. gcc/ChangeLog: 2021-01-15 Jonathan Wright * config/aarch64/aarch64-simd-builtins.def: Add mls_n builtin generator macro. * config/aarch64/aarch64-simd.md (*aarch64_mls_elt_merge): Rename to... (aarch64_mls_n): This. * config/aarch64/arm_neon.h (vmls_n_s16): Use RTL builtin instead of asm. (vmls_n_s32): Likewise. (vmls_n_u16): Likewise. (vmls_n_u32): Likewise. (vmlsq_n_s16): Likewise. (vmlsq_n_s32): Likewise. (vmlsq_n_u16): Likewise. (vmlsq_n_u32): Likewise. --- gcc/config/aarch64/aarch64-simd-builtins.def | 2 + gcc/config/aarch64/aarch64-simd.md | 11 ++-- gcc/config/aarch64/arm_neon.h | 64 +++++--------------- 3 files changed, 24 insertions(+), 53 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 93a087987bb..32aee6024a8 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -185,6 +185,8 @@ /* Implemented by aarch64_mls. */ BUILTIN_VDQ_BHSI (TERNOP, mls, 0, NONE) + /* Implemented by aarch64_mls_n. */ + BUILTIN_VDQHS (TERNOP, mls_n, 0, NONE) /* Implemented by aarch64_mlsl. */ BUILTIN_VD_BHSI (TERNOP, smlsl, 0, NONE) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 693a6187105..544bac7dc9b 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1443,15 +1443,16 @@ [(set_attr "type" "neon_mla__scalar")] ) -(define_insn "*aarch64_mls_elt_merge" +(define_insn "aarch64_mls_n" [(set (match_operand:VDQHS 0 "register_operand" "=w") (minus:VDQHS (match_operand:VDQHS 1 "register_operand" "0") - (mult:VDQHS (vec_duplicate:VDQHS - (match_operand: 2 "register_operand" "")) - (match_operand:VDQHS 3 "register_operand" "w"))))] + (mult:VDQHS + (vec_duplicate:VDQHS + (match_operand: 3 "register_operand" "")) + (match_operand:VDQHS 2 "register_operand" "w"))))] "TARGET_SIMD" - "mls\t%0., %3., %2.[0]" + "mls\t%0., %2., %3.[0]" [(set_attr "type" "neon_mla__scalar")] ) diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 45b3c125bab..d891067f021 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -7840,48 +7840,32 @@ __extension__ extern __inline int16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmls_n_s16 (int16x4_t __a, int16x4_t __b, int16_t __c) { - int16x4_t __result; - __asm__ ("mls %0.4h, %2.4h, %3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mls_nv4hi (__a, __b, __c); } __extension__ extern __inline int32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmls_n_s32 (int32x2_t __a, int32x2_t __b, int32_t __c) { - int32x2_t __result; - __asm__ ("mls %0.2s, %2.2s, %3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mls_nv2si (__a, __b, __c); } __extension__ extern __inline uint16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmls_n_u16 (uint16x4_t __a, uint16x4_t __b, uint16_t __c) { - uint16x4_t __result; - __asm__ ("mls %0.4h, %2.4h, %3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return (uint16x4_t) __builtin_aarch64_mls_nv4hi ((int16x4_t) __a, + (int16x4_t) __b, + (int16_t) __c); } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmls_n_u32 (uint32x2_t __a, uint32x2_t __b, uint32_t __c) { - uint32x2_t __result; - __asm__ ("mls %0.2s, %2.2s, %3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return (uint32x2_t) __builtin_aarch64_mls_nv2si ((int32x2_t) __a, + (int32x2_t) __b, + (int32_t) __c); } __extension__ extern __inline int8x8_t @@ -8353,48 +8337,32 @@ __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsq_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c) { - int16x8_t __result; - __asm__ ("mls %0.8h, %2.8h, %3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mls_nv8hi (__a, __b, __c); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsq_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c) { - int32x4_t __result; - __asm__ ("mls %0.4s, %2.4s, %3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mls_nv4si (__a, __b, __c); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsq_n_u16 (uint16x8_t __a, uint16x8_t __b, uint16_t __c) { - uint16x8_t __result; - __asm__ ("mls %0.8h, %2.8h, %3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return (uint16x8_t) __builtin_aarch64_mls_nv8hi ((int16x8_t) __a, + (int16x8_t) __b, + (int16_t) __c); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsq_n_u32 (uint32x4_t __a, uint32x4_t __b, uint32_t __c) { - uint32x4_t __result; - __asm__ ("mls %0.4s, %2.4s, %3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return (uint32x4_t) __builtin_aarch64_mls_nv4si ((int32x4_t) __a, + (int32x4_t) __b, + (int32_t) __c); } __extension__ extern __inline int8x16_t -- 2.30.2