From 3fdbf0687e4f7d43ee3a984f3d6229f89f7d0a3b Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 8 May 2023 12:41:12 +0100 Subject: [PATCH] --- openpower/sv/cr_ops.mdwn | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn index 7ee59bc94..902bd73c2 100644 --- a/openpower/sv/cr_ops.mdwn +++ b/openpower/sv/cr_ops.mdwn @@ -75,12 +75,12 @@ Field result *is* the main result. SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations: -|6 | 7 |19-20| 21 | 22 23 | description | -|--|---|-----| --- |---------|----------------- | -|/ | / |0 RG | 0 | dz sz | simple mode | -|/ | / |0 RG | 1 | dz sz | scalar reduce mode (mapreduce) | -|zz|SNZ|1 VLI| inv | CR-bit | Ffirst 3-bit mode | -|/ |SNZ|1 VLI| inv | dz sz | Ffirst 5-bit mode (implies CR-bit from result) | +|6 | 7 |19-20|21 | 22 23 | description | +|--|---|-----|---|---------|------------------| +|/ | / |0 RG | 0 | dz sz | simple mode | +|/ | / |0 RG | 1 | dz sz | scalar reduce mode (mapreduce) | +|zz|SNZ|1 VLI|inv| CR-bit | Ffirst 3-bit mode | +|/ |SNZ|1 VLI|inv| dz sz | Ffirst 5-bit mode (implies CR-bit from result) | Fields: -- 2.30.2