From 3fe8476c8575946d9c17136067d72b998d4c38bb Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Mon, 7 Aug 2023 16:04:00 -0700 Subject: [PATCH] split out instructions from openpower/isa/fixedshift.mdwn --- openpower/isa/fixedshift.mdwn | 367 +------------------- openpower/isa/fixedshift/extswsli.mdwn | 16 + openpower/isa/fixedshift/extswsli_code.mdwn | 4 + openpower/isa/fixedshift/rldcl.mdwn | 14 + openpower/isa/fixedshift/rldcl_code.mdwn | 5 + openpower/isa/fixedshift/rldcr.mdwn | 14 + openpower/isa/fixedshift/rldcr_code.mdwn | 5 + openpower/isa/fixedshift/rldic.mdwn | 14 + openpower/isa/fixedshift/rldic_code.mdwn | 5 + openpower/isa/fixedshift/rldicl.mdwn | 14 + openpower/isa/fixedshift/rldicl_code.mdwn | 5 + openpower/isa/fixedshift/rldicr.mdwn | 14 + openpower/isa/fixedshift/rldicr_code.mdwn | 5 + openpower/isa/fixedshift/rldimi.mdwn | 17 + openpower/isa/fixedshift/rldimi_code.mdwn | 5 + openpower/isa/fixedshift/rlwimi.mdwn | 14 + openpower/isa/fixedshift/rlwimi_code.mdwn | 4 + openpower/isa/fixedshift/rlwinm.mdwn | 14 + openpower/isa/fixedshift/rlwinm_code.mdwn | 4 + openpower/isa/fixedshift/rlwnm.mdwn | 14 + openpower/isa/fixedshift/rlwnm_code.mdwn | 4 + openpower/isa/fixedshift/sld.mdwn | 14 + openpower/isa/fixedshift/sld_code.mdwn | 6 + openpower/isa/fixedshift/slw.mdwn | 14 + openpower/isa/fixedshift/slw_code.mdwn | 6 + openpower/isa/fixedshift/srad.mdwn | 15 + openpower/isa/fixedshift/srad_code.mdwn | 10 + openpower/isa/fixedshift/sradi.mdwn | 15 + openpower/isa/fixedshift/sradi_code.mdwn | 8 + openpower/isa/fixedshift/sraw.mdwn | 15 + openpower/isa/fixedshift/sraw_code.mdwn | 10 + openpower/isa/fixedshift/srawi.mdwn | 15 + openpower/isa/fixedshift/srawi_code.mdwn | 8 + openpower/isa/fixedshift/srd.mdwn | 14 + openpower/isa/fixedshift/srd_code.mdwn | 6 + openpower/isa/fixedshift/srw.mdwn | 14 + openpower/isa/fixedshift/srw_code.mdwn | 6 + 37 files changed, 385 insertions(+), 349 deletions(-) create mode 100644 openpower/isa/fixedshift/extswsli.mdwn create mode 100644 openpower/isa/fixedshift/extswsli_code.mdwn create mode 100644 openpower/isa/fixedshift/rldcl.mdwn create mode 100644 openpower/isa/fixedshift/rldcl_code.mdwn create mode 100644 openpower/isa/fixedshift/rldcr.mdwn create mode 100644 openpower/isa/fixedshift/rldcr_code.mdwn create mode 100644 openpower/isa/fixedshift/rldic.mdwn create mode 100644 openpower/isa/fixedshift/rldic_code.mdwn create mode 100644 openpower/isa/fixedshift/rldicl.mdwn create mode 100644 openpower/isa/fixedshift/rldicl_code.mdwn create mode 100644 openpower/isa/fixedshift/rldicr.mdwn create mode 100644 openpower/isa/fixedshift/rldicr_code.mdwn create mode 100644 openpower/isa/fixedshift/rldimi.mdwn create mode 100644 openpower/isa/fixedshift/rldimi_code.mdwn create mode 100644 openpower/isa/fixedshift/rlwimi.mdwn create mode 100644 openpower/isa/fixedshift/rlwimi_code.mdwn create mode 100644 openpower/isa/fixedshift/rlwinm.mdwn create mode 100644 openpower/isa/fixedshift/rlwinm_code.mdwn create mode 100644 openpower/isa/fixedshift/rlwnm.mdwn create mode 100644 openpower/isa/fixedshift/rlwnm_code.mdwn create mode 100644 openpower/isa/fixedshift/sld.mdwn create mode 100644 openpower/isa/fixedshift/sld_code.mdwn create mode 100644 openpower/isa/fixedshift/slw.mdwn create mode 100644 openpower/isa/fixedshift/slw_code.mdwn create mode 100644 openpower/isa/fixedshift/srad.mdwn create mode 100644 openpower/isa/fixedshift/srad_code.mdwn create mode 100644 openpower/isa/fixedshift/sradi.mdwn create mode 100644 openpower/isa/fixedshift/sradi_code.mdwn create mode 100644 openpower/isa/fixedshift/sraw.mdwn create mode 100644 openpower/isa/fixedshift/sraw_code.mdwn create mode 100644 openpower/isa/fixedshift/srawi.mdwn create mode 100644 openpower/isa/fixedshift/srawi_code.mdwn create mode 100644 openpower/isa/fixedshift/srd.mdwn create mode 100644 openpower/isa/fixedshift/srd_code.mdwn create mode 100644 openpower/isa/fixedshift/srw.mdwn create mode 100644 openpower/isa/fixedshift/srw_code.mdwn diff --git a/openpower/isa/fixedshift.mdwn b/openpower/isa/fixedshift.mdwn index db59a6fa..bd0911f6 100644 --- a/openpower/isa/fixedshift.mdwn +++ b/openpower/isa/fixedshift.mdwn @@ -10,369 +10,38 @@ -# Rotate Left Word Immediate then AND with Mask +[[!inline pagenames="openpower/isa/fixedshift/rlwinm" raw="yes"]] -M-Form +[[!inline pagenames="openpower/isa/fixedshift/rlwnm" raw="yes"]] -* rlwinm RA,RS,SH,MB,ME (Rc=0) -* rlwinm. RA,RS,SH,MB,ME (Rc=1) +[[!inline pagenames="openpower/isa/fixedshift/rlwimi" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/fixedshift/rldicl" raw="yes"]] - n <- SH - r <- ROTL32((RS)[XLEN/2:XLEN-1], n) - m <- MASK32(MB, ME) - RA <- r & m +[[!inline pagenames="openpower/isa/fixedshift/rldicr" raw="yes"]] -Special Registers Altered: +[[!inline pagenames="openpower/isa/fixedshift/rldic" raw="yes"]] - CR0 (if Rc=1) +[[!inline pagenames="openpower/isa/fixedshift/rldcl" raw="yes"]] -# Rotate Left Word then AND with Mask +[[!inline pagenames="openpower/isa/fixedshift/rldcr" raw="yes"]] -M-Form +[[!inline pagenames="openpower/isa/fixedshift/rldimi" raw="yes"]] -* rlwnm RA,RS,RB,MB,ME (Rc=0) -* rlwnm. RA,RS,RB,MB,ME (Rc=1) +[[!inline pagenames="openpower/isa/fixedshift/slw" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/fixedshift/srw" raw="yes"]] - n <- (RB)[XLEN-5:XLEN-1] - r <- ROTL32((RS)[XLEN/2:XLEN-1], n) - m <- MASK32(MB, ME) - RA <- r & m +[[!inline pagenames="openpower/isa/fixedshift/srawi" raw="yes"]] -Special Registers Altered: +[[!inline pagenames="openpower/isa/fixedshift/sraw" raw="yes"]] - CR0 (if Rc=1) +[[!inline pagenames="openpower/isa/fixedshift/sld" raw="yes"]] -# Rotate Left Word Immediate then Mask Insert +[[!inline pagenames="openpower/isa/fixedshift/srd" raw="yes"]] -M-Form +[[!inline pagenames="openpower/isa/fixedshift/sradi" raw="yes"]] -* rlwimi RA,RS,SH,MB,ME (Rc=0) -* rlwimi. RA,RS,SH,MB,ME (Rc=1) +[[!inline pagenames="openpower/isa/fixedshift/srad" raw="yes"]] -Pseudo-code: - - n <- SH - r <- ROTL32((RS)[XLEN/2:XLEN-1], n) - m <- MASK32(MB, ME) - RA <- r&m | (RA) & ¬m - -Special Registers Altered: - - CR0 (if Rc=1) - -# Rotate Left Doubleword Immediate then Clear Left - -MD-Form - -* rldicl RA,RS,sh,mb (Rc=0) -* rldicl. RA,RS,sh,mb (Rc=1) - -Pseudo-code: - - n <- sh - r <- ROTL64((RS), n) - b <- mb[5] || mb[0:4] - m <- MASK(b, (XLEN-1)) - RA <- r & m - -Special Registers Altered: - - CR0 (if Rc=1) - -# Rotate Left Doubleword Immediate then Clear Right - -MD-Form - -* rldicr RA,RS,sh,me (Rc=0) -* rldicr. RA,RS,sh,me (Rc=1) - -Pseudo-code: - - n <- sh - r <- ROTL64((RS), n) - e <- me[5] || me[0:4] - m <- MASK(0, e) - RA <- r & m - -Special Registers Altered: - - CR0 (if Rc=1) - -# Rotate Left Doubleword Immediate then Clear - -MD-Form - -* rldic RA,RS,sh,mb (Rc=0) -* rldic. RA,RS,sh,mb (Rc=1) - -Pseudo-code: - - n <- sh - r <- ROTL64((RS), n) - b <- mb[5] || mb[0:4] - m <- MASK(b, ¬n) - RA <- r & m - -Special Registers Altered: - - CR0 (if Rc=1) - -# Rotate Left Doubleword then Clear Left - -MDS-Form - -* rldcl RA,RS,RB,mb (Rc=0) -* rldcl. RA,RS,RB,mb (Rc=1) - -Pseudo-code: - - n <- (RB)[XLEN-5:XLEN-1] - r <- ROTL64((RS), n) - b <- mb[5] || mb[0:4] - m <- MASK(b, (XLEN-1)) - RA <- r & m - -Special Registers Altered: - - CR0 (if Rc=1) - -# Rotate Left Doubleword then Clear Right - -MDS-Form - -* rldcr RA,RS,RB,me (Rc=0) -* rldcr. RA,RS,RB,me (Rc=1) - -Pseudo-code: - - n <- (RB)[XLEN-5:XLEN-1] - r <- ROTL64((RS), n) - e <- me[5] || me[0:4] - m <- MASK(0, e) - RA <- r & m - -Special Registers Altered: - - CR0 (if Rc=1) - -# Rotate Left Doubleword Immediate then Mask Insert - -MD-Form - -* rldimi RA,RS,sh,mb (Rc=0) -* rldimi. RA,RS,sh,mb (Rc=1) - -Pseudo-code: - - n <- sh - r <- ROTL64((RS), n) - b <- mb[5] || mb[0:4] - m <- MASK(b, ¬n) - RA <- r&m | (RA)& ¬m - -Special Registers Altered: - - CR0 (if Rc=1) - - - - -# Shift Left Word - -X-Form - -* slw RA,RS,RB (Rc=0) -* slw. RA,RS,RB (Rc=1) - -Pseudo-code: - - n <- (RB)[XLEN-5:XLEN-1] - r <- ROTL32((RS)[XLEN/2:XLEN-1], n) - if (RB)[XLEN-6] = 0 then - m <- MASK32(0, ((XLEN/2)-1-n)) - else m <- [0]*XLEN - RA <- r & m - -Special Registers Altered: - - CR0 (if Rc=1) - -# Shift Right Word - -X-Form - -* srw RA,RS,RB (Rc=0) -* srw. RA,RS,RB (Rc=1) - -Pseudo-code: - - n <- (RB)[XLEN-5:XLEN-1] - r <- ROTL32((RS)[XLEN/2:XLEN-1], XLEN-n) - if (RB)[XLEN-6] = 0 then - m <- MASK32(n, ((XLEN/2)-1)) - else m <- [0]*XLEN - RA <- r & m - -Special Registers Altered: - - CR0 (if Rc=1) - -# Shift Right Algebraic Word Immediate - -X-Form - -* srawi RA,RS,SH (Rc=0) -* srawi. RA,RS,SH (Rc=1) - -Pseudo-code: - - n <- SH - r <- ROTL32((RS)[XLEN/2:XLEN-1], 64-n) - m <- MASK32(n, ((XLEN/2)-1)) - s <- (RS)[XLEN/2] - RA <- r&m | ([s]*XLEN)& ¬m - carry <- s & ((r&¬m)[XLEN/2:XLEN-1] != 0) - CA <- carry - CA32 <- carry - -Special Registers Altered: - - CA CA32 - CR0 (if Rc=1) - -# Shift Right Algebraic Word - -X-Form - -* sraw RA,RS,RB (Rc=0) -* sraw. RA,RS,RB (Rc=1) - -Pseudo-code: - - n <- (RB)[XLEN-5:XLEN-1] - r <- ROTL32((RS)[XLEN/2:XLEN-1], XLEN-n) - if (RB)[XLEN-6] = 0 then - m <- MASK32(n, ((XLEN/2)-1)) - else m <- [0]*XLEN - s <- (RS)[XLEN/2] - RA <- r&m | ([s]*XLEN)& ¬m - carry <- s & ((r&¬m)[XLEN/2:XLEN-1] != 0) - CA <- carry - CA32 <- carry - -Special Registers Altered: - - CA CA32 - CR0 (if Rc=1) - -# Shift Left Doubleword - -X-Form - -* sld RA,RS,RB (Rc=0) -* sld. RA,RS,RB (Rc=1) - -Pseudo-code: - - n <- (RB)[XLEN-6:XLEN-1] - r <- ROTL64((RS), n) - if (RB)[XLEN-7] = 0 then - m <- MASK(0, XLEN-1-n) - else m <- [0]*XLEN - RA <- r & m - -Special Registers Altered: - - CR0 (if Rc=1) - -# Shift Right Doubleword - -X-Form - -* srd RA,RS,RB (Rc=0) -* srd. RA,RS,RB (Rc=1) - -Pseudo-code: - - n <- (RB)[XLEN-6:XLEN-1] - r <- ROTL64((RS), XLEN-n) - if (RB)[XLEN-7] = 0 then - m <- MASK(n, (XLEN-1)) - else m <- [0]*XLEN - RA <- r & m - -Special Registers Altered: - - CR0 (if Rc=1) - -# Shift Right Algebraic Doubleword Immediate - -XS-Form - -* sradi RA,RS,sh (Rc=0) -* sradi. RA,RS,sh (Rc=1) - -Pseudo-code: - - n <- sh - r <- ROTL64((RS), XLEN-n) - m <- MASK(n, (XLEN-1)) - s <- (RS)[0] - RA <- r&m | ([s]*XLEN)& ¬m - carry <- s & ((r& ¬m) != 0) - CA <- carry - CA32 <- carry - -Special Registers Altered: - - CA CA32 - CR0 (if Rc=1) - -# Shift Right Algebraic Doubleword - -X-Form - -* srad RA,RS,RB (Rc=0) -* srad. RA,RS,RB (Rc=1) - -Pseudo-code: - - n <- (RB)[XLEN-6:XLEN-1] - r <- ROTL64((RS), XLEN-n) - if (RB)[XLEN-7] = 0 then - m <- MASK(n, (XLEN-1)) - else m <- [0]*XLEN - s <- (RS)[0] - RA <- r&m | ([s]*XLEN)& ¬m - carry <- s & ((r&¬m) != 0) - CA <- carry - CA32 <- carry - -Special Registers Altered: - - CA CA32 - CR0 (if Rc=1) - -# Extend-Sign Word and Shift Left Immediate - -XS-Form - -* extswsli RA,RS,sh (Rc=0) -* extswsli. RA,RS,sh (Rc=1) - -Pseudo-code: - - n <- sh - r <- ROTL64(EXTS64(RS[XLEN/2:XLEN-1]), n) - m <- MASK(0, XLEN-1-n) - RA <- r & m - -Special Registers Altered: - - CR0 (if Rc=1) - - +[[!inline pagenames="openpower/isa/fixedshift/extswsli" raw="yes"]] diff --git a/openpower/isa/fixedshift/extswsli.mdwn b/openpower/isa/fixedshift/extswsli.mdwn new file mode 100644 index 00000000..28a08ed0 --- /dev/null +++ b/openpower/isa/fixedshift/extswsli.mdwn @@ -0,0 +1,16 @@ +# Extend-Sign Word and Shift Left Immediate + +XS-Form + +* extswsli RA,RS,sh (Rc=0) +* extswsli. RA,RS,sh (Rc=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedshift/extswsli_code" raw="yes"]] + +Special Registers Altered: + + CR0 (if Rc=1) + + diff --git a/openpower/isa/fixedshift/extswsli_code.mdwn b/openpower/isa/fixedshift/extswsli_code.mdwn new file mode 100644 index 00000000..d859fc0b --- /dev/null +++ b/openpower/isa/fixedshift/extswsli_code.mdwn @@ -0,0 +1,4 @@ + n <- sh + r <- ROTL64(EXTS64(RS[XLEN/2:XLEN-1]), n) + m <- MASK(0, XLEN-1-n) + RA <- r & m diff --git a/openpower/isa/fixedshift/rldcl.mdwn b/openpower/isa/fixedshift/rldcl.mdwn new file mode 100644 index 00000000..c780043f --- /dev/null +++ b/openpower/isa/fixedshift/rldcl.mdwn @@ -0,0 +1,14 @@ +# Rotate Left Doubleword then Clear Left + +MDS-Form + +* rldcl RA,RS,RB,mb (Rc=0) +* rldcl. RA,RS,RB,mb (Rc=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedshift/rldcl_code" raw="yes"]] + +Special Registers Altered: + + CR0 (if Rc=1) diff --git a/openpower/isa/fixedshift/rldcl_code.mdwn b/openpower/isa/fixedshift/rldcl_code.mdwn new file mode 100644 index 00000000..ec6cee3c --- /dev/null +++ b/openpower/isa/fixedshift/rldcl_code.mdwn @@ -0,0 +1,5 @@ + n <- (RB)[XLEN-5:XLEN-1] + r <- ROTL64((RS), n) + b <- mb[5] || mb[0:4] + m <- MASK(b, (XLEN-1)) + RA <- r & m diff --git a/openpower/isa/fixedshift/rldcr.mdwn b/openpower/isa/fixedshift/rldcr.mdwn new file mode 100644 index 00000000..3da31074 --- /dev/null +++ b/openpower/isa/fixedshift/rldcr.mdwn @@ -0,0 +1,14 @@ +# Rotate Left Doubleword then Clear Right + +MDS-Form + +* rldcr RA,RS,RB,me (Rc=0) +* rldcr. RA,RS,RB,me (Rc=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedshift/rldcr_code" raw="yes"]] + +Special Registers Altered: + + CR0 (if Rc=1) diff --git a/openpower/isa/fixedshift/rldcr_code.mdwn b/openpower/isa/fixedshift/rldcr_code.mdwn new file mode 100644 index 00000000..9889d102 --- /dev/null +++ b/openpower/isa/fixedshift/rldcr_code.mdwn @@ -0,0 +1,5 @@ + n <- (RB)[XLEN-5:XLEN-1] + r <- ROTL64((RS), n) + e <- me[5] || me[0:4] + m <- MASK(0, e) + RA <- r & m diff --git a/openpower/isa/fixedshift/rldic.mdwn b/openpower/isa/fixedshift/rldic.mdwn new file mode 100644 index 00000000..33907b0b --- /dev/null +++ b/openpower/isa/fixedshift/rldic.mdwn @@ -0,0 +1,14 @@ +# Rotate Left Doubleword Immediate then Clear + +MD-Form + +* rldic RA,RS,sh,mb (Rc=0) +* rldic. RA,RS,sh,mb (Rc=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedshift/rldic_code" raw="yes"]] + +Special Registers Altered: + + CR0 (if Rc=1) diff --git a/openpower/isa/fixedshift/rldic_code.mdwn b/openpower/isa/fixedshift/rldic_code.mdwn new file mode 100644 index 00000000..ea492227 --- /dev/null +++ b/openpower/isa/fixedshift/rldic_code.mdwn @@ -0,0 +1,5 @@ + n <- sh + r <- ROTL64((RS), n) + b <- mb[5] || mb[0:4] + m <- MASK(b, ¬n) + RA <- r & m diff --git a/openpower/isa/fixedshift/rldicl.mdwn b/openpower/isa/fixedshift/rldicl.mdwn new file mode 100644 index 00000000..ff039f8b --- /dev/null +++ b/openpower/isa/fixedshift/rldicl.mdwn @@ -0,0 +1,14 @@ +# Rotate Left Doubleword Immediate then Clear Left + +MD-Form + +* rldicl RA,RS,sh,mb (Rc=0) +* rldicl. RA,RS,sh,mb (Rc=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedshift/rldicl_code" raw="yes"]] + +Special Registers Altered: + + CR0 (if Rc=1) diff --git a/openpower/isa/fixedshift/rldicl_code.mdwn b/openpower/isa/fixedshift/rldicl_code.mdwn new file mode 100644 index 00000000..a59670ca --- /dev/null +++ b/openpower/isa/fixedshift/rldicl_code.mdwn @@ -0,0 +1,5 @@ + n <- sh + r <- ROTL64((RS), n) + b <- mb[5] || mb[0:4] + m <- MASK(b, (XLEN-1)) + RA <- r & m diff --git a/openpower/isa/fixedshift/rldicr.mdwn b/openpower/isa/fixedshift/rldicr.mdwn new file mode 100644 index 00000000..10af0d61 --- /dev/null +++ b/openpower/isa/fixedshift/rldicr.mdwn @@ -0,0 +1,14 @@ +# Rotate Left Doubleword Immediate then Clear Right + +MD-Form + +* rldicr RA,RS,sh,me (Rc=0) +* rldicr. RA,RS,sh,me (Rc=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedshift/rldicr_code" raw="yes"]] + +Special Registers Altered: + + CR0 (if Rc=1) diff --git a/openpower/isa/fixedshift/rldicr_code.mdwn b/openpower/isa/fixedshift/rldicr_code.mdwn new file mode 100644 index 00000000..5ade62a4 --- /dev/null +++ b/openpower/isa/fixedshift/rldicr_code.mdwn @@ -0,0 +1,5 @@ + n <- sh + r <- ROTL64((RS), n) + e <- me[5] || me[0:4] + m <- MASK(0, e) + RA <- r & m diff --git a/openpower/isa/fixedshift/rldimi.mdwn b/openpower/isa/fixedshift/rldimi.mdwn new file mode 100644 index 00000000..90583628 --- /dev/null +++ b/openpower/isa/fixedshift/rldimi.mdwn @@ -0,0 +1,17 @@ +# Rotate Left Doubleword Immediate then Mask Insert + +MD-Form + +* rldimi RA,RS,sh,mb (Rc=0) +* rldimi. RA,RS,sh,mb (Rc=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedshift/rldimi_code" raw="yes"]] + +Special Registers Altered: + + CR0 (if Rc=1) + + + diff --git a/openpower/isa/fixedshift/rldimi_code.mdwn b/openpower/isa/fixedshift/rldimi_code.mdwn new file mode 100644 index 00000000..ad44a52e --- /dev/null +++ b/openpower/isa/fixedshift/rldimi_code.mdwn @@ -0,0 +1,5 @@ + n <- sh + r <- ROTL64((RS), n) + b <- mb[5] || mb[0:4] + m <- MASK(b, ¬n) + RA <- r&m | (RA)& ¬m diff --git a/openpower/isa/fixedshift/rlwimi.mdwn b/openpower/isa/fixedshift/rlwimi.mdwn new file mode 100644 index 00000000..44a6c604 --- /dev/null +++ b/openpower/isa/fixedshift/rlwimi.mdwn @@ -0,0 +1,14 @@ +# Rotate Left Word Immediate then Mask Insert + +M-Form + +* rlwimi RA,RS,SH,MB,ME (Rc=0) +* rlwimi. RA,RS,SH,MB,ME (Rc=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedshift/rlwimi_code" raw="yes"]] + +Special Registers Altered: + + CR0 (if Rc=1) diff --git a/openpower/isa/fixedshift/rlwimi_code.mdwn b/openpower/isa/fixedshift/rlwimi_code.mdwn new file mode 100644 index 00000000..f27808be --- /dev/null +++ b/openpower/isa/fixedshift/rlwimi_code.mdwn @@ -0,0 +1,4 @@ + n <- SH + r <- ROTL32((RS)[XLEN/2:XLEN-1], n) + m <- MASK32(MB, ME) + RA <- r&m | (RA) & ¬m diff --git a/openpower/isa/fixedshift/rlwinm.mdwn b/openpower/isa/fixedshift/rlwinm.mdwn new file mode 100644 index 00000000..ca1cc4a7 --- /dev/null +++ b/openpower/isa/fixedshift/rlwinm.mdwn @@ -0,0 +1,14 @@ +# Rotate Left Word Immediate then AND with Mask + +M-Form + +* rlwinm RA,RS,SH,MB,ME (Rc=0) +* rlwinm. RA,RS,SH,MB,ME (Rc=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedshift/rlwinm_code" raw="yes"]] + +Special Registers Altered: + + CR0 (if Rc=1) diff --git a/openpower/isa/fixedshift/rlwinm_code.mdwn b/openpower/isa/fixedshift/rlwinm_code.mdwn new file mode 100644 index 00000000..2311947f --- /dev/null +++ b/openpower/isa/fixedshift/rlwinm_code.mdwn @@ -0,0 +1,4 @@ + n <- SH + r <- ROTL32((RS)[XLEN/2:XLEN-1], n) + m <- MASK32(MB, ME) + RA <- r & m diff --git a/openpower/isa/fixedshift/rlwnm.mdwn b/openpower/isa/fixedshift/rlwnm.mdwn new file mode 100644 index 00000000..0bd03b89 --- /dev/null +++ b/openpower/isa/fixedshift/rlwnm.mdwn @@ -0,0 +1,14 @@ +# Rotate Left Word then AND with Mask + +M-Form + +* rlwnm RA,RS,RB,MB,ME (Rc=0) +* rlwnm. RA,RS,RB,MB,ME (Rc=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedshift/rlwnm_code" raw="yes"]] + +Special Registers Altered: + + CR0 (if Rc=1) diff --git a/openpower/isa/fixedshift/rlwnm_code.mdwn b/openpower/isa/fixedshift/rlwnm_code.mdwn new file mode 100644 index 00000000..d49d3cec --- /dev/null +++ b/openpower/isa/fixedshift/rlwnm_code.mdwn @@ -0,0 +1,4 @@ + n <- (RB)[XLEN-5:XLEN-1] + r <- ROTL32((RS)[XLEN/2:XLEN-1], n) + m <- MASK32(MB, ME) + RA <- r & m diff --git a/openpower/isa/fixedshift/sld.mdwn b/openpower/isa/fixedshift/sld.mdwn new file mode 100644 index 00000000..95328329 --- /dev/null +++ b/openpower/isa/fixedshift/sld.mdwn @@ -0,0 +1,14 @@ +# Shift Left Doubleword + +X-Form + +* sld RA,RS,RB (Rc=0) +* sld. RA,RS,RB (Rc=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedshift/sld_code" raw="yes"]] + +Special Registers Altered: + + CR0 (if Rc=1) diff --git a/openpower/isa/fixedshift/sld_code.mdwn b/openpower/isa/fixedshift/sld_code.mdwn new file mode 100644 index 00000000..c9614101 --- /dev/null +++ b/openpower/isa/fixedshift/sld_code.mdwn @@ -0,0 +1,6 @@ + n <- (RB)[XLEN-6:XLEN-1] + r <- ROTL64((RS), n) + if (RB)[XLEN-7] = 0 then + m <- MASK(0, XLEN-1-n) + else m <- [0]*XLEN + RA <- r & m diff --git a/openpower/isa/fixedshift/slw.mdwn b/openpower/isa/fixedshift/slw.mdwn new file mode 100644 index 00000000..f6c5ae68 --- /dev/null +++ b/openpower/isa/fixedshift/slw.mdwn @@ -0,0 +1,14 @@ +# Shift Left Word + +X-Form + +* slw RA,RS,RB (Rc=0) +* slw. RA,RS,RB (Rc=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedshift/slw_code" raw="yes"]] + +Special Registers Altered: + + CR0 (if Rc=1) diff --git a/openpower/isa/fixedshift/slw_code.mdwn b/openpower/isa/fixedshift/slw_code.mdwn new file mode 100644 index 00000000..308b21f2 --- /dev/null +++ b/openpower/isa/fixedshift/slw_code.mdwn @@ -0,0 +1,6 @@ + n <- (RB)[XLEN-5:XLEN-1] + r <- ROTL32((RS)[XLEN/2:XLEN-1], n) + if (RB)[XLEN-6] = 0 then + m <- MASK32(0, ((XLEN/2)-1-n)) + else m <- [0]*XLEN + RA <- r & m diff --git a/openpower/isa/fixedshift/srad.mdwn b/openpower/isa/fixedshift/srad.mdwn new file mode 100644 index 00000000..7c014b47 --- /dev/null +++ b/openpower/isa/fixedshift/srad.mdwn @@ -0,0 +1,15 @@ +# Shift Right Algebraic Doubleword + +X-Form + +* srad RA,RS,RB (Rc=0) +* srad. RA,RS,RB (Rc=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedshift/srad_code" raw="yes"]] + +Special Registers Altered: + + CA CA32 + CR0 (if Rc=1) diff --git a/openpower/isa/fixedshift/srad_code.mdwn b/openpower/isa/fixedshift/srad_code.mdwn new file mode 100644 index 00000000..96ab99d8 --- /dev/null +++ b/openpower/isa/fixedshift/srad_code.mdwn @@ -0,0 +1,10 @@ + n <- (RB)[XLEN-6:XLEN-1] + r <- ROTL64((RS), XLEN-n) + if (RB)[XLEN-7] = 0 then + m <- MASK(n, (XLEN-1)) + else m <- [0]*XLEN + s <- (RS)[0] + RA <- r&m | ([s]*XLEN)& ¬m + carry <- s & ((r&¬m) != 0) + CA <- carry + CA32 <- carry diff --git a/openpower/isa/fixedshift/sradi.mdwn b/openpower/isa/fixedshift/sradi.mdwn new file mode 100644 index 00000000..4fe2651a --- /dev/null +++ b/openpower/isa/fixedshift/sradi.mdwn @@ -0,0 +1,15 @@ +# Shift Right Algebraic Doubleword Immediate + +XS-Form + +* sradi RA,RS,sh (Rc=0) +* sradi. RA,RS,sh (Rc=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedshift/sradi_code" raw="yes"]] + +Special Registers Altered: + + CA CA32 + CR0 (if Rc=1) diff --git a/openpower/isa/fixedshift/sradi_code.mdwn b/openpower/isa/fixedshift/sradi_code.mdwn new file mode 100644 index 00000000..4e886f87 --- /dev/null +++ b/openpower/isa/fixedshift/sradi_code.mdwn @@ -0,0 +1,8 @@ + n <- sh + r <- ROTL64((RS), XLEN-n) + m <- MASK(n, (XLEN-1)) + s <- (RS)[0] + RA <- r&m | ([s]*XLEN)& ¬m + carry <- s & ((r& ¬m) != 0) + CA <- carry + CA32 <- carry diff --git a/openpower/isa/fixedshift/sraw.mdwn b/openpower/isa/fixedshift/sraw.mdwn new file mode 100644 index 00000000..2cd99551 --- /dev/null +++ b/openpower/isa/fixedshift/sraw.mdwn @@ -0,0 +1,15 @@ +# Shift Right Algebraic Word + +X-Form + +* sraw RA,RS,RB (Rc=0) +* sraw. RA,RS,RB (Rc=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedshift/sraw_code" raw="yes"]] + +Special Registers Altered: + + CA CA32 + CR0 (if Rc=1) diff --git a/openpower/isa/fixedshift/sraw_code.mdwn b/openpower/isa/fixedshift/sraw_code.mdwn new file mode 100644 index 00000000..9f170436 --- /dev/null +++ b/openpower/isa/fixedshift/sraw_code.mdwn @@ -0,0 +1,10 @@ + n <- (RB)[XLEN-5:XLEN-1] + r <- ROTL32((RS)[XLEN/2:XLEN-1], XLEN-n) + if (RB)[XLEN-6] = 0 then + m <- MASK32(n, ((XLEN/2)-1)) + else m <- [0]*XLEN + s <- (RS)[XLEN/2] + RA <- r&m | ([s]*XLEN)& ¬m + carry <- s & ((r&¬m)[XLEN/2:XLEN-1] != 0) + CA <- carry + CA32 <- carry diff --git a/openpower/isa/fixedshift/srawi.mdwn b/openpower/isa/fixedshift/srawi.mdwn new file mode 100644 index 00000000..5fbfa1b0 --- /dev/null +++ b/openpower/isa/fixedshift/srawi.mdwn @@ -0,0 +1,15 @@ +# Shift Right Algebraic Word Immediate + +X-Form + +* srawi RA,RS,SH (Rc=0) +* srawi. RA,RS,SH (Rc=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedshift/srawi_code" raw="yes"]] + +Special Registers Altered: + + CA CA32 + CR0 (if Rc=1) diff --git a/openpower/isa/fixedshift/srawi_code.mdwn b/openpower/isa/fixedshift/srawi_code.mdwn new file mode 100644 index 00000000..9aa79248 --- /dev/null +++ b/openpower/isa/fixedshift/srawi_code.mdwn @@ -0,0 +1,8 @@ + n <- SH + r <- ROTL32((RS)[XLEN/2:XLEN-1], 64-n) + m <- MASK32(n, ((XLEN/2)-1)) + s <- (RS)[XLEN/2] + RA <- r&m | ([s]*XLEN)& ¬m + carry <- s & ((r&¬m)[XLEN/2:XLEN-1] != 0) + CA <- carry + CA32 <- carry diff --git a/openpower/isa/fixedshift/srd.mdwn b/openpower/isa/fixedshift/srd.mdwn new file mode 100644 index 00000000..fded2c8e --- /dev/null +++ b/openpower/isa/fixedshift/srd.mdwn @@ -0,0 +1,14 @@ +# Shift Right Doubleword + +X-Form + +* srd RA,RS,RB (Rc=0) +* srd. RA,RS,RB (Rc=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedshift/srd_code" raw="yes"]] + +Special Registers Altered: + + CR0 (if Rc=1) diff --git a/openpower/isa/fixedshift/srd_code.mdwn b/openpower/isa/fixedshift/srd_code.mdwn new file mode 100644 index 00000000..a7608123 --- /dev/null +++ b/openpower/isa/fixedshift/srd_code.mdwn @@ -0,0 +1,6 @@ + n <- (RB)[XLEN-6:XLEN-1] + r <- ROTL64((RS), XLEN-n) + if (RB)[XLEN-7] = 0 then + m <- MASK(n, (XLEN-1)) + else m <- [0]*XLEN + RA <- r & m diff --git a/openpower/isa/fixedshift/srw.mdwn b/openpower/isa/fixedshift/srw.mdwn new file mode 100644 index 00000000..6f553209 --- /dev/null +++ b/openpower/isa/fixedshift/srw.mdwn @@ -0,0 +1,14 @@ +# Shift Right Word + +X-Form + +* srw RA,RS,RB (Rc=0) +* srw. RA,RS,RB (Rc=1) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedshift/srw_code" raw="yes"]] + +Special Registers Altered: + + CR0 (if Rc=1) diff --git a/openpower/isa/fixedshift/srw_code.mdwn b/openpower/isa/fixedshift/srw_code.mdwn new file mode 100644 index 00000000..473038d1 --- /dev/null +++ b/openpower/isa/fixedshift/srw_code.mdwn @@ -0,0 +1,6 @@ + n <- (RB)[XLEN-5:XLEN-1] + r <- ROTL32((RS)[XLEN/2:XLEN-1], XLEN-n) + if (RB)[XLEN-6] = 0 then + m <- MASK32(n, ((XLEN/2)-1)) + else m <- [0]*XLEN + RA <- r & m -- 2.30.2