From 3ff1bcaf0526929f9972bb94024cb265a61864af Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 30 Jul 2020 21:37:25 +0200
Subject: [PATCH] cpu/zynq7000: set csr map to 0x00000000.

---
 litex/soc/cores/cpu/zynq7000/core.py | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/litex/soc/cores/cpu/zynq7000/core.py b/litex/soc/cores/cpu/zynq7000/core.py
index 9ed783a8..91d7692e 100644
--- a/litex/soc/cores/cpu/zynq7000/core.py
+++ b/litex/soc/cores/cpu/zynq7000/core.py
@@ -24,6 +24,10 @@ class Zynq7000(CPU):
     nop                  = "nop"
     io_regions           = {0x00000000: 0x100000000} # origin, length
 
+    @property
+    def mem_map(self):
+        return {"csr": 0x00000000}
+
     def __init__(self, platform, variant):
         self.platform       = platform
         self.reset          = Signal()
-- 
2.30.2