From 40018e191b7f5e233b2da4eab823f37d51a07778 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 26 Jan 2022 16:52:36 +0100 Subject: [PATCH] Display values of outputs --- passes/sat/sim.cc | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 605dc8e1e..8cabcfbb4 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -885,6 +885,7 @@ struct SimWorker : SimShared SigMap sigmap(topmod); log ("Get inputs\n"); std::map inputs; + std::map outputs; for (auto wire : topmod->wires()) { if (wire->port_input) { @@ -892,6 +893,11 @@ struct SimWorker : SimShared log("Input %s\n",log_id(wire)); inputs[wire] = id; } + if (wire->port_output) { + fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name)); + log("Output %s %d\n",log_id(wire), id); + outputs[wire] = id; + } } fst->reconstruct(fst_clock); @@ -903,19 +909,11 @@ struct SimWorker : SimShared top->set_state(item.first, Const::from_string(v)); } update(); - - /*Wire *wire = topmod->wire("\\cnt"); - Const value = top->get_state(wire); - std::stringstream ss; - for (int i = GetSize(value)-1; i >= 0; i--) { - switch (value[i]) { - case State::S0: ss << "0"; break; - case State::S1: ss << "1"; break; - case State::Sx: ss << "x"; break; - default: ss << "z"; - } + for(auto &item : outputs) { + Const fst_val = Const::from_string(fst->valueAt(item.second, time)); + Const sim_val = top->get_state(item.first); + log("%s %s\n", log_signal(fst_val), log_signal(sim_val)); } - log("%s\n",ss.str().c_str());*/ } } }; -- 2.30.2