From 402f2ac63933c7f9f096bf9afb6a945adbd920d4 Mon Sep 17 00:00:00 2001 From: Sandipan Das Date: Thu, 7 Jun 2018 11:14:41 +0530 Subject: [PATCH] arch-power: Add fields for DX form instructions This introduces the extended opcode field and the fields d0, d1 and d2 for DX form instructions. Change-Id: Iac52bca39993e4a5f299f33d356e36037c516130 Signed-off-by: Sandipan Das --- src/arch/power/isa/bitfields.isa | 1 + src/arch/power/types.hh | 3 +++ 2 files changed, 4 insertions(+) diff --git a/src/arch/power/isa/bitfields.isa b/src/arch/power/isa/bitfields.isa index fcf592f8a..dcecdd40e 100644 --- a/src/arch/power/isa/bitfields.isa +++ b/src/arch/power/isa/bitfields.isa @@ -39,6 +39,7 @@ def bitfield PO <31:26>; def bitfield A_XO <5:1>; def bitfield DS_XO <1:0>; +def bitfield DX_XO <5:1>; def bitfield X_XO <10:1>; def bitfield XFL_XO <10:1>; def bitfield XFX_XO <10:1>; diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh index 929f765e0..8f499bbf1 100644 --- a/src/arch/power/types.hh +++ b/src/arch/power/types.hh @@ -55,6 +55,9 @@ BitUnion32(ExtMachInst) Bitfield<15, 0> si; Bitfield<15, 0> d; Bitfield<15, 2> ds; + Bitfield<15, 6> d0; + Bitfield<20, 16> d1; + Bitfield< 1, 0> d2; // Special purpose register identifier Bitfield<20, 11> spr; -- 2.30.2