From 40342404f2ca4f55a65aaf98949b8459c49b01b0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 23 Apr 2019 06:43:48 +0200 Subject: [PATCH] cores/clock: add divclk_divide_range on S6PLL/S6DCM --- litex/soc/cores/clock.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py index e496673d..5757ad75 100644 --- a/litex/soc/cores/clock.py +++ b/litex/soc/cores/clock.py @@ -126,6 +126,7 @@ class S6PLL(XilinxClocking): def __init__(self, speedgrade=-1): XilinxClocking.__init__(self) + self.divclk_divide_range = (1, 52 + 1) self.vco_freq_range = { -1: (400e6, 1000e6), -2: (400e6, 1000e6), @@ -164,6 +165,7 @@ class S6DCM(XilinxClocking): def __init__(self, speedgrade=-1): XilinxClocking.__init__(self) + self.divclk_divide_range = (1, 1) # FIXME self.clkin_freq_range = { -1: (0.5e6, 200e6), -2: (0.5e6, 333e6), -- 2.30.2