From 403d25ad385cd2e8a1fb1a80f95969b7b10e2b7b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 27 Jun 2020 17:50:07 +0100 Subject: [PATCH] fix TestMemLoadStoreUnit, it required a FSM to monitor write and also needed to honour the "busy_o" signal --- src/soc/config/test/test_pi2ls.py | 4 ++-- src/soc/experiment/lsmem.py | 19 +++++++++++++++++-- 2 files changed, 19 insertions(+), 4 deletions(-) diff --git a/src/soc/config/test/test_pi2ls.py b/src/soc/config/test/test_pi2ls.py index f064d5e1..0c39532d 100644 --- a/src/soc/config/test/test_pi2ls.py +++ b/src/soc/config/test/test_pi2ls.py @@ -59,11 +59,11 @@ def l0_cache_st(dut, addr, data, datalen): yield port1.pi.st.ok.eq(1) yield yield port1.pi.st.ok.eq(0) + yield from wait_busy(port1, True) # wait while busy # can go straight to reset. yield port1.pi.is_st_i.eq(0) # end yield port1.pi.addr.ok.eq(0) # set !ok - # yield from wait_busy(port1, False) # wait until not busy def l0_cache_ld(dut, addr, datalen): @@ -91,7 +91,7 @@ def l0_cache_ld(dut, addr, datalen): # cleanup yield port1.pi.is_ld_i.eq(0) # end yield port1.pi.addr.ok.eq(0) # set !ok - # yield from wait_busy(port1, no=False) # wait until not busy + yield from wait_busy(port1, no=False) # wait while not busy return data diff --git a/src/soc/experiment/lsmem.py b/src/soc/experiment/lsmem.py index da9c73ac..08764232 100644 --- a/src/soc/experiment/lsmem.py +++ b/src/soc/experiment/lsmem.py @@ -22,14 +22,29 @@ class TestMemLoadStoreUnit(LoadStoreUnitInterface, Elaboratable): do_load.eq(self.x_ld_i & (self.x_valid_i & ~self.x_stall_i)), do_store.eq(self.x_st_i & (self.x_valid_i & ~self.x_stall_i)), ] + # bit of a messy FSM that progresses from idle to in progress + # to done. + op_actioned = Signal(reset=0) + op_in_progress = Signal(reset=0) + with m.If(~op_actioned & (do_load | do_store)): # idle + m.d.sync += op_actioned.eq(1) + m.d.sync += op_in_progress.eq(1) + with m.Elif(op_in_progress): # in progress + m.d.sync += op_actioned.eq(0) + with m.If(~(do_load | do_store)): # done + m.d.sync += op_in_progress.eq(0) + + m.d.comb += self.x_busy_o.eq(op_actioned & self.x_valid_i) + m.d.comb += [ # load mem.rdport.addr.eq(self.x_addr_i[adr_lsb:]), self.m_ld_data_o.eq(mem.rdport.data), - # store + # store - only activates once mem.wrport.addr.eq(self.x_addr_i[adr_lsb:]), - mem.wrport.en.eq(Mux(do_store, self.x_mask_i, 0)), + mem.wrport.en.eq(Mux(do_store & ~op_actioned, + self.x_mask_i, 0)), mem.wrport.data.eq(self.x_st_data_i) ] -- 2.30.2