From 404b86813e73762cdce537c440abb16f6ab1bb97 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Tue, 23 Jul 2019 16:34:26 +0100 Subject: [PATCH] dev-arm: TnSZ fields need to be cached in SMMUv3::ConfigCache Otherwise a hit after a table walk will result in a 0 value being read from the ConfigCache. Change-Id: I9813998acce44c93c5ce203f252ca80c10ba8f38 Signed-off-by: Giacomo Travaglini Reviewed-by: Michiel Van Tol Reviewed-by: Adrian Herrera Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19631 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg Tested-by: kokoro --- src/dev/arm/smmu_v3_caches.hh | 2 ++ src/dev/arm/smmu_v3_transl.cc | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/src/dev/arm/smmu_v3_caches.hh b/src/dev/arm/smmu_v3_caches.hh index ce5bb45a9..060f60e11 100644 --- a/src/dev/arm/smmu_v3_caches.hh +++ b/src/dev/arm/smmu_v3_caches.hh @@ -252,6 +252,8 @@ class ConfigCache : public SMMUv3BaseCache uint16_t vmid; uint8_t stage1_tg; uint8_t stage2_tg; + uint8_t t0sz; + uint8_t s2t0sz; }; ConfigCache(unsigned numEntries, unsigned _associativity, diff --git a/src/dev/arm/smmu_v3_transl.cc b/src/dev/arm/smmu_v3_transl.cc index 84ca5a7c2..c1d998ea0 100644 --- a/src/dev/arm/smmu_v3_transl.cc +++ b/src/dev/arm/smmu_v3_transl.cc @@ -532,6 +532,9 @@ SMMUTranslationProcess::configCacheLookup(Yield &yield, TranslContext &tc) tc.stage1TranslGranule = e->stage1_tg; tc.stage2TranslGranule = e->stage2_tg; + tc.t0sz = e->t0sz; + tc.s2t0sz = e->s2t0sz; + return true; } @@ -555,6 +558,8 @@ SMMUTranslationProcess::configCacheUpdate(Yield &yield, e.vmid = tc.vmid; e.stage1_tg = tc.stage1TranslGranule; e.stage2_tg = tc.stage2TranslGranule; + e.t0sz = tc.t0sz; + e.s2t0sz = tc.s2t0sz; doSemaphoreDown(yield, smmu.configSem); -- 2.30.2