From 404def8928b5746573e24dc31c6fd6ec5b07d97f Mon Sep 17 00:00:00 2001 From: Tsukasa OI Date: Mon, 24 Oct 2022 15:05:58 +0000 Subject: [PATCH] RISC-V: Add stub support for the 'Svadu' extension This commit implements support for 'Svadu' extension. Because it does not add any instructions or CSRs (but adds bits to existing CSRs), this commit only adds extension name support and implication to the 'Zicsr' extension. This is based on the "Hardware Updating of PTE A/D Bits (Svadu)" specification, version 1.0-rc1 (Frozen): bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Add implication from 'Svadu' to 'Zicsr'. (riscv_supported_std_s_ext) Add 'Svadu'. --- bfd/elfxx-riscv.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index ff61a601ca2..e642a05fe5b 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1190,6 +1190,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"sscofpmf", "zicsr", check_implicit_always}, {"ssstateen", "zicsr", check_implicit_always}, {"sstc", "zicsr", check_implicit_always}, + {"svadu", "zicsr", check_implicit_always}, {NULL, NULL, NULL} }; @@ -1336,6 +1337,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] = {"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sstc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"svadu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svinval", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svnapot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svpbmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -- 2.30.2