From 404f524fe2a3e3cc0024b3b8f8dc2e592a8aafed Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sat, 29 Jul 2017 22:03:38 +0200 Subject: [PATCH] radeonsi: don't flush sL1 conditionally in WAIT_ON_CE_COUNTER MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit I don't know the condition for the flush, but we better turn this off. The sL1 flush is used when CE dumps stuff into a ring buffer and the ring buffer wraps. Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_state_draw.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index a5f5b7f98a0..dfe423610bf 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -1145,10 +1145,10 @@ void si_ce_pre_draw_synchronization(struct si_context *sctx) { if (sctx->ce_need_synchronization) { radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0)); - radeon_emit(sctx->ce_ib, 1); + radeon_emit(sctx->ce_ib, 1); /* 1 = increment CE counter */ radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0)); - radeon_emit(sctx->b.gfx.cs, 1); + radeon_emit(sctx->b.gfx.cs, 0); /* 0 = don't flush sL1 conditionally */ } } @@ -1156,7 +1156,7 @@ void si_ce_post_draw_synchronization(struct si_context *sctx) { if (sctx->ce_need_synchronization) { radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0)); - radeon_emit(sctx->b.gfx.cs, 0); + radeon_emit(sctx->b.gfx.cs, 0); /* unused */ sctx->ce_need_synchronization = false; } -- 2.30.2