From 40568763016cbd09aa2e682575946e1bf04f2c73 Mon Sep 17 00:00:00 2001 From: Nils Asmussen Date: Sat, 21 Mar 2020 11:02:41 +0100 Subject: [PATCH] configs: added bare metal FS support for RISC-V. Change-Id: Id412186d868680b9af97503a5337fc394fd84f68 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26989 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- configs/common/FSConfig.py | 24 ++++++++++++++++++++++++ configs/example/fs.py | 8 +++++++- 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index 7fc5557f9..d49ad78e7 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -1,4 +1,5 @@ # Copyright (c) 2010-2012, 2015-2019 ARM Limited +# Copyright (c) 2020 Barkhausen Institut # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -48,6 +49,7 @@ from common import ObjectList # Populate to reflect supported os types per target ISA os_types = { 'mips' : [ 'linux' ], + 'riscv' : [ 'linux' ], # TODO that's a lie 'sparc' : [ 'linux' ], 'x86' : [ 'linux' ], 'arm' : [ 'linux', @@ -614,6 +616,28 @@ def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False, self.workload.command_line = fillInCmdline(mdesc, cmdline) return self +def makeBareMetalRiscvSystem(mem_mode, mdesc=None, cmdline=None): + self = System() + if not mdesc: + # generic system + mdesc = SysConfig() + self.mem_mode = mem_mode + self.mem_ranges = [AddrRange(mdesc.mem())] + + self.workload = RiscvBareMetal() + + self.iobus = IOXBar() + self.membus = MemBus() + + self.bridge = Bridge(delay='50ns') + self.bridge.master = self.iobus.slave + self.bridge.slave = self.membus.master + # Sv39 has 56 bit physical addresses; use the upper 8 bit for the IO space + IO_address_space_base = 0x00FF000000000000 + self.bridge.ranges = [AddrRange(IO_address_space_base, Addr.max)] + + self.system_port = self.membus.slave + return self def makeDualRoot(full_system, testSystem, driveSystem, dumpfile): self = Root(full_system = full_system) diff --git a/configs/example/fs.py b/configs/example/fs.py index 5264aa568..6643d35c4 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -1,4 +1,5 @@ # Copyright (c) 2010-2013, 2016, 2019 ARM Limited +# Copyright (c) 2020 Barkhausen Institut # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -82,6 +83,9 @@ def build_test_system(np): test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) + elif buildEnv['TARGET_ISA'] == "riscv": + test_sys = makeBareMetalRiscvSystem(test_mem_mode, bm[0], + cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "x86": test_sys = makeLinuxX86System(test_mem_mode, np, bm[0], options.ruby, cmdline=cmdline) @@ -123,7 +127,9 @@ def build_test_system(np): voltage_domain = test_sys.cpu_voltage_domain) - if options.kernel is not None: + if buildEnv['TARGET_ISA'] == 'riscv': + test_sys.workload.bootloader = options.kernel + elif options.kernel is not None: test_sys.workload.object_file = binary(options.kernel) if options.script is not None: -- 2.30.2